i965: Enable EGL_KHR_gl_texture_3D_image

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_sampler_state.c

diff --git a/src/mesa/drivers/dri/i965/gen6_sampler_state.c b/src/mesa/drivers/dri/i965/gen6_sampler_state.c
index ab8e7516d23b23095dd5efd00bb90af2c3d061f8..b5a0c92b3ba67f56cb161437157d5839249ac992 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sampler_state.c
@@ -33,39 +33,25 @@
 static void
 upload_sampler_state_pointers(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-
    BEGIN_BATCH(4);
-   OUT_BATCH(CMD_3D_SAMPLER_STATE_POINTERS << 16 |
+   OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 |
             VS_SAMPLER_STATE_CHANGE |
             GS_SAMPLER_STATE_CHANGE |
             PS_SAMPLER_STATE_CHANGE |
             (4 - 2));
-   OUT_BATCH(0); /* VS */
-   OUT_BATCH(0); /* GS */
-   if (brw->wm.sampler_bo)
-      OUT_RELOC(brw->wm.sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-   else
-      OUT_BATCH(0);
-
+   OUT_BATCH(brw->vs.base.sampler_offset); /* VS */
+   OUT_BATCH(brw->gs.base.sampler_offset); /* GS */
+   OUT_BATCH(brw->wm.base.sampler_offset);
    ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
-}
-
-
-static void
-prepare_sampler_state_pointers(struct brw_context *brw)
-{
-   brw_add_validated_bo(brw, brw->wm.sampler_bo);
 }
 
 const struct brw_tracked_state gen6_sampler_state = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_BATCH,
-      .cache = CACHE_NEW_SAMPLER
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_BLORP |
+             BRW_NEW_SAMPLER_STATE_TABLE |
+             BRW_NEW_STATE_BASE_ADDRESS,
    },
-   .prepare = prepare_sampler_state_pointers,
    .emit = upload_sampler_state_pointers,
 };