i965/fs: Add support for translating ir_triop_fma into MAD.

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_scissor_state.c

diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
index d0b37a078d5638ca79d67256872c1b64ec4fd865..7b92b7cb1764e918e926366d6de6591317d05a7a 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
@@ -29,17 +29,18 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "intel_batchbuffer.h"
+#include "main/fbobject.h"
 
 static void
-gen6_prepare_scissor_state(struct brw_context *brw)
+gen6_upload_scissor_state(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
-   const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
+   struct gl_context *ctx = &brw->ctx;
+   const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
    struct gen6_scissor_rect *scissor;
    uint32_t scissor_state_offset;
 
-   scissor = brw_state_batch(brw, sizeof(*scissor), 32, &scissor_state_offset);
+   scissor = brw_state_batch(brw, AUB_TRACE_SCISSOR_STATE,
+                            sizeof(*scissor), 32, &scissor_state_offset);
 
    /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
 
@@ -79,8 +80,7 @@ gen6_prepare_scissor_state(struct brw_context *brw)
 
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
-   OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
-            scissor_state_offset);
+   OUT_BATCH(scissor_state_offset);
    ADVANCE_BATCH();
 }
 
@@ -90,5 +90,5 @@ const struct brw_tracked_state gen6_scissor_state = {
       .brw = BRW_NEW_BATCH,
       .cache = 0,
    },
-   .prepare = gen6_prepare_scissor_state,
+   .emit = gen6_upload_scissor_state,
 };