i965/fs: Handle fixed HW GRF subnr in reg_offset().

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_scissor_state.c

diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
index 12b65826ae99a98531f1258e99c6c43194546953..b03ac730a3ea52065745cc5f39f1acb1c653f717 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
@@ -29,13 +29,22 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "intel_batchbuffer.h"
+#include "main/fbobject.h"
+#include "main/framebuffer.h"
 
 static void
-prepare_scissor_state(struct brw_context *brw)
+gen6_upload_scissor_state(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->intel.ctx;
-   const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
-   struct gen6_scissor_rect scissor;
+   struct gl_context *ctx = &brw->ctx;
+   const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
+   struct gen6_scissor_rect *scissor;
+   uint32_t scissor_state_offset;
+   const unsigned int fb_width= _mesa_geometric_width(ctx->DrawBuffer);
+   const unsigned int fb_height = _mesa_geometric_height(ctx->DrawBuffer);
+
+   scissor = brw_state_batch(brw, AUB_TRACE_SCISSOR_STATE,
+                            sizeof(*scissor) * ctx->Const.MaxViewports, 32,
+                             &scissor_state_offset);
 
    /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
 
@@ -46,70 +55,54 @@ prepare_scissor_state(struct brw_context *brw)
     * Note that the hardware's coordinates are inclusive, while Mesa's min is
     * inclusive but max is exclusive.
     */
-   if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
-       ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
-      /* If the scissor was out of bounds and got clamped to 0
-       * width/height at the bounds, the subtraction of 1 from
-       * maximums could produce a negative number and thus not clip
-       * anything.  Instead, just provide a min > max scissor inside
-       * the bounds, which produces the expected no rendering.
-       */
-      scissor.xmin = 1;
-      scissor.xmax = 0;
-      scissor.ymin = 1;
-      scissor.ymax = 0;
-   } else if (render_to_fbo) {
-      /* texmemory: Y=0=bottom */
-      scissor.xmin = ctx->DrawBuffer->_Xmin;
-      scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
-      scissor.ymin = ctx->DrawBuffer->_Ymin;
-      scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
-   }
-   else {
-      /* memory: Y=0=top */
-      scissor.xmin = ctx->DrawBuffer->_Xmin;
-      scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
-      scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
-      scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
-   }
-
-   drm_intel_bo_unreference(brw->sf.state_bo);
-   brw->sf.state_bo = brw_cache_data(&brw->cache, BRW_SF_UNIT,
-                                    &scissor, sizeof(scissor));
-}
-
-const struct brw_tracked_state gen6_scissor_state = {
-   .dirty = {
-      .mesa = _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT,
-      .brw = 0,
-      .cache = 0,
-   },
-   .prepare = prepare_scissor_state,
-};
+   for (unsigned i = 0; i < ctx->Const.MaxViewports; i++) {
+      int bbox[4];
 
-static void upload_scissor_state_pointers(struct brw_context *brw)
-{
-   struct intel_context *intel = &brw->intel;
+      bbox[0] = MAX2(ctx->ViewportArray[i].X, 0);
+      bbox[1] = MIN2(bbox[0] + ctx->ViewportArray[i].Width, fb_width);
+      bbox[2] = MAX2(ctx->ViewportArray[i].Y, 0);
+      bbox[3] = MIN2(bbox[2] + ctx->ViewportArray[i].Height, fb_height);
+      _mesa_intersect_scissor_bounding_box(ctx, i, bbox);
 
+      if (bbox[0] == bbox[1] || bbox[2] == bbox[3]) {
+         /* If the scissor was out of bounds and got clamped to 0 width/height
+          * at the bounds, the subtraction of 1 from maximums could produce a
+          * negative number and thus not clip anything.  Instead, just provide
+          * a min > max scissor inside the bounds, which produces the expected
+          * no rendering.
+          */
+         scissor[i].xmin = 1;
+         scissor[i].xmax = 0;
+         scissor[i].ymin = 1;
+         scissor[i].ymax = 0;
+      } else if (render_to_fbo) {
+         /* texmemory: Y=0=bottom */
+         scissor[i].xmin = bbox[0];
+         scissor[i].xmax = bbox[1] - 1;
+         scissor[i].ymin = bbox[2];
+         scissor[i].ymax = bbox[3] - 1;
+      }
+      else {
+         /* memory: Y=0=top */
+         scissor[i].xmin = bbox[0];
+         scissor[i].xmax = bbox[1] - 1;
+         scissor[i].ymin = fb_height - bbox[3];
+         scissor[i].ymax = fb_height - bbox[2] - 1;
+      }
+   }
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
-   OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+   OUT_BATCH(scissor_state_offset);
    ADVANCE_BATCH();
-
 }
 
-
-static void prepare_scissor_state_pointers(struct brw_context *brw)
-{
-   brw_add_validated_bo(brw, brw->sf.state_bo);
-}
-
-const struct brw_tracked_state gen6_scissor_state_pointers = {
+const struct brw_tracked_state gen6_scissor_state = {
    .dirty = {
-      .mesa = 0,
-      .brw = BRW_NEW_BATCH,
-      .cache = CACHE_NEW_SF_UNIT
+      .mesa = _NEW_BUFFERS |
+              _NEW_SCISSOR |
+              _NEW_VIEWPORT,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_BLORP,
    },
-   .prepare = prepare_scissor_state_pointers,
-   .emit = upload_scissor_state_pointers,
+   .emit = gen6_upload_scissor_state,
 };