i965: Make the old VS backend record pull constant references in pull_params[].
[mesa.git] / src / mesa / drivers / dri / i965 / gen6_scissor_state.c
index 2e21e5f733573f4c235ae4c9a130995e772c8516..dc73b10f4cd74c1c479313b70439d0c93c894f94 100644 (file)
 #include "intel_batchbuffer.h"
 
 static void
-prepare_scissor_state(struct brw_context *brw)
+gen6_upload_scissor_state(struct brw_context *brw)
 {
-   GLcontext *ctx = &brw->intel.ctx;
+   struct intel_context *intel = &brw->intel;
+   struct gl_context *ctx = &intel->ctx;
    const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
-   struct gen6_scissor_state scissor;
+   struct gen6_scissor_rect *scissor;
+   uint32_t scissor_state_offset;
+
+   scissor = brw_state_batch(brw, AUB_TRACE_SCISSOR_STATE,
+                            sizeof(*scissor), 32, &scissor_state_offset);
 
    /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
 
@@ -46,60 +51,44 @@ prepare_scissor_state(struct brw_context *brw)
     * Note that the hardware's coordinates are inclusive, while Mesa's min is
     * inclusive but max is exclusive.
     */
-   if (render_to_fbo) {
+   if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
+       ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
+      /* If the scissor was out of bounds and got clamped to 0
+       * width/height at the bounds, the subtraction of 1 from
+       * maximums could produce a negative number and thus not clip
+       * anything.  Instead, just provide a min > max scissor inside
+       * the bounds, which produces the expected no rendering.
+       */
+      scissor->xmin = 1;
+      scissor->xmax = 0;
+      scissor->ymin = 1;
+      scissor->ymax = 0;
+   } else if (render_to_fbo) {
       /* texmemory: Y=0=bottom */
-      scissor.xmin = ctx->DrawBuffer->_Xmin;
-      scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
-      scissor.ymin = ctx->DrawBuffer->_Ymin;
-      scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
+      scissor->xmin = ctx->DrawBuffer->_Xmin;
+      scissor->xmax = ctx->DrawBuffer->_Xmax - 1;
+      scissor->ymin = ctx->DrawBuffer->_Ymin;
+      scissor->ymax = ctx->DrawBuffer->_Ymax - 1;
    }
    else {
       /* memory: Y=0=top */
-      scissor.xmin = ctx->DrawBuffer->_Xmin;
-      scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
-      scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
-      scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
+      scissor->xmin = ctx->DrawBuffer->_Xmin;
+      scissor->xmax = ctx->DrawBuffer->_Xmax - 1;
+      scissor->ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
+      scissor->ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
    }
 
-   drm_intel_bo_unreference(brw->sf.state_bo);
-   brw->sf.state_bo = brw_cache_data(&brw->cache, BRW_SF_UNIT,
-                                    &scissor, sizeof(scissor),
-                                    NULL, 0);
-}
-
-const struct brw_tracked_state gen6_scissor_state = {
-   .dirty = {
-      .mesa = _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT,
-      .brw = 0,
-      .cache = 0,
-   },
-   .prepare = prepare_scissor_state,
-};
-
-static void upload_scissor_state_pointers(struct brw_context *brw)
-{
-   struct intel_context *intel = &brw->intel;
-
    BEGIN_BATCH(2);
-   OUT_BATCH(CMD_3D_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
-   OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+   OUT_BATCH(_3DSTATE_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
+   OUT_BATCH(scissor_state_offset);
    ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
-
-static void prepare_scissor_state_pointers(struct brw_context *brw)
-{
-   brw_add_validated_bo(brw, brw->sf.state_bo);
-}
-
-const struct brw_tracked_state gen6_scissor_state_pointers = {
+const struct brw_tracked_state gen6_scissor_state = {
    .dirty = {
-      .mesa = 0,
+      .mesa = _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT,
       .brw = BRW_NEW_BATCH,
-      .cache = CACHE_NEW_SF_UNIT
+      .cache = 0,
    },
-   .prepare = prepare_scissor_state_pointers,
-   .emit = upload_scissor_state_pointers,
+   .emit = gen6_upload_scissor_state,
 };