intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_sol.c

diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c b/src/mesa/drivers/dri/i965/gen6_sol.c
index cdd6e74c8652eaf680c9c7f450b61fd7c6f6ff77..5c294b1d768e31dfe5c4cd2451f2e5f24783f154 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -36,7 +36,7 @@
 static void
 gen6_update_sol_surfaces(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->intel.ctx;
+   struct gl_context *ctx = &brw->ctx;
    /* BRW_NEW_TRANSFORM_FEEDBACK */
    struct gl_transform_feedback_object *xfb_obj =
       ctx->TransformFeedback.CurrentObject;
@@ -85,7 +85,7 @@ const struct brw_tracked_state gen6_sol_surface = {
 static void
 brw_gs_upload_binding_table(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->intel.ctx;
+   struct gl_context *ctx = &brw->ctx;
    /* BRW_NEW_VERTEX_PROGRAM */
    const struct gl_shader_program *shaderprog =
       ctx->Shader.CurrentVertexProgram;
@@ -137,7 +137,6 @@ brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
                             struct gl_transform_feedback_object *obj)
 {
    struct brw_context *brw = brw_context(ctx);
-   struct intel_context *intel = &brw->intel;
    const struct gl_shader_program *vs_prog =
       ctx->Shader.CurrentVertexProgram;
    const struct gl_transform_feedback_info *linked_xfb_info =
@@ -145,6 +144,8 @@ brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
    struct gl_transform_feedback_object *xfb_obj =
       ctx->TransformFeedback.CurrentObject;
 
+   assert(brw->gen == 6);
+
    /* Compute the maximum number of vertices that we can write without
     * overflowing any of the buffers currently being used for feedback.
     */
@@ -152,36 +153,25 @@ brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
       = _mesa_compute_max_transform_feedback_vertices(xfb_obj,
                                                       linked_xfb_info);
 
-   if (intel->gen == 6) {
-      /* Initialize the SVBI 0 register to zero and set the maximum index. */
+   /* Initialize the SVBI 0 register to zero and set the maximum index. */
+   BEGIN_BATCH(4);
+   OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
+   OUT_BATCH(0); /* SVBI 0 */
+   OUT_BATCH(0); /* starting index */
+   OUT_BATCH(max_index);
+   ADVANCE_BATCH();
+
+   /* Initialize the rest of the unused streams to sane values.  Otherwise,
+    * they may indicate that there is no room to write data and prevent
+    * anything from happening at all.
+    */
+   for (int i = 1; i < 4; i++) {
       BEGIN_BATCH(4);
       OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
-      OUT_BATCH(0); /* SVBI 0 */
+      OUT_BATCH(i << SVB_INDEX_SHIFT);
       OUT_BATCH(0); /* starting index */
-      OUT_BATCH(max_index);
+      OUT_BATCH(0xffffffff);
       ADVANCE_BATCH();
-
-      /* Initialize the rest of the unused streams to sane values.  Otherwise,
-       * they may indicate that there is no room to write data and prevent
-       * anything from happening at all.
-       */
-      for (int i = 1; i < 4; i++) {
-         BEGIN_BATCH(4);
-         OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
-         OUT_BATCH(i << SVB_INDEX_SHIFT);
-         OUT_BATCH(0); /* starting index */
-         OUT_BATCH(0xffffffff);
-         ADVANCE_BATCH();
-      }
-   } else if (intel->gen >= 7) {
-      /* Reset the SOL buffer offset register. */
-      for (int i = 0; i < 4; i++) {
-         BEGIN_BATCH(3);
-         OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
-         OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
-         OUT_BATCH(0);
-         ADVANCE_BATCH();
-      }
    }
 }
 
@@ -196,6 +186,5 @@ brw_end_transform_feedback(struct gl_context *ctx,
     * simplicity, just do a full flush.
     */
    struct brw_context *brw = brw_context(ctx);
-   struct intel_context *intel = &brw->intel;
-   intel_batchbuffer_emit_mi_flush(intel);
+   intel_batchbuffer_emit_mi_flush(brw);
 }