i965: Silence unused parameter warnings in intel_mipmap_tree.c
[mesa.git] / src / mesa / drivers / dri / i965 / gen6_surface_state.c
index 0980fd1557b59df866eb7b332f0eb7e0b41ea0e9..39de62f2304b12d94176d32a93caedd6a6e74884 100644 (file)
@@ -26,6 +26,7 @@
 #include "main/blend.h"
 #include "main/mtypes.h"
 #include "main/samplerobj.h"
+#include "main/texformat.h"
 #include "program/prog_parameter.h"
 
 #include "intel_mipmap_tree.h"
  * While it is only used for the front/back buffer currently, it should be
  * usable for further buffers when doing ARB_draw_buffer support.
  */
-static void
+static uint32_t
 gen6_update_renderbuffer_surface(struct brw_context *brw,
                                  struct gl_renderbuffer *rb,
-                                 bool layered,
-                                 unsigned int unit)
+                                 bool layered, unsigned unit /* unused */,
+                                 uint32_t surf_index)
 {
    struct gl_context *ctx = &brw->ctx;
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
    struct intel_mipmap_tree *mt = irb->mt;
    uint32_t *surf;
-   uint32_t tile_x, tile_y;
    uint32_t format = 0;
+   uint32_t offset;
    /* _NEW_BUFFERS */
    mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
-   uint32_t surf_index =
-      brw->wm.prog_data->binding_table.render_target_start + unit;
-
-   assert(!layered);
-
-   if (rb->TexImage && !brw->has_surface_tile_offset) {
-      intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y);
-
-      if (tile_x != 0 || tile_y != 0) {
-        /* Original gen4 hardware couldn't draw to a non-tile-aligned
-         * destination in a miptree unless you actually setup your renderbuffer
-         * as a miptree and used the fragile lod/array_index/etc. controls to
-         * select the image.  So, instead, we just make a new single-level
-         * miptree and render into that.
-         */
-        intel_renderbuffer_move_to_temp(brw, irb, false);
-        mt = irb->mt;
-      }
-   }
+   uint32_t surftype;
+   int depth = MAX2(irb->layer_count, 1);
+   const GLenum gl_target =
+      rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 
    intel_miptree_used_for_rendering(irb->mt);
 
-   surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
-                          &brw->wm.base.surf_offset[surf_index]);
+   surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset);
 
    format = brw->render_target_format[rb_format];
    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
-                    __FUNCTION__, _mesa_get_format_name(rb_format));
+                    __func__, _mesa_get_format_name(rb_format));
+   }
+
+   switch (gl_target) {
+   case GL_TEXTURE_CUBE_MAP_ARRAY:
+   case GL_TEXTURE_CUBE_MAP:
+      surftype = BRW_SURFACE_2D;
+      depth *= 6;
+      break;
+   case GL_TEXTURE_3D:
+      depth = MAX2(irb->mt->logical_depth0, 1);
+      /* fallthrough */
+   default:
+      surftype = translate_tex_target(gl_target);
+      break;
    }
 
-   surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
-             format << BRW_SURFACE_FORMAT_SHIFT);
+   const int min_array_element = irb->mt_layer;
+   assert(!layered || irb->mt_layer == 0);
+
+   surf[0] = SET_FIELD(surftype, BRW_SURFACE_TYPE) |
+             SET_FIELD(format, BRW_SURFACE_FORMAT);
 
    /* reloc */
-   surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
-             mt->bo->offset64);
+   assert(mt->offset % mt->cpp == 0);
+   surf[1] = mt->bo->offset64 + mt->offset;
+
+   /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
+    * (Surface Arrays For all surfaces other than separate stencil buffer):
+    *
+    * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
+    *  calculated in the equation above , for every other odd Surface Height
+    *  starting from 1 i.e. 1,5,9,13"
+    *
+    * Since this Qpitch errata only impacts the sampler, we have to adjust the
+    * input for the rendering surface to achieve the same qpitch. For the
+    * affected heights, we increment the height by 1 for the rendering
+    * surface.
+    */
+   int height0 = irb->mt->logical_height0;
+   if (brw->gen == 6 && irb->mt->num_samples > 1 && (height0 % 4) == 1)
+      height0++;
 
-   surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
-             (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
+   surf[2] = SET_FIELD(mt->logical_width0 - 1, BRW_SURFACE_WIDTH) |
+             SET_FIELD(height0 - 1, BRW_SURFACE_HEIGHT) |
+             SET_FIELD(irb->mt_level - irb->mt->first_level, BRW_SURFACE_LOD);
 
-   surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
-             (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
+   surf[3] = brw_get_surface_tiling_bits(mt->tiling) |
+             SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
+             SET_FIELD(mt->pitch - 1, BRW_SURFACE_PITCH);
 
-   surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
+   surf[4] = brw_get_surface_num_multisamples(mt->num_samples) |
+             SET_FIELD(min_array_element, BRW_SURFACE_MIN_ARRAY_ELEMENT) |
+             SET_FIELD(depth - 1, BRW_SURFACE_RENDER_TARGET_VIEW_EXTENT);
 
-   assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
-   /* Note that the low bits of these fields are missing, so
-    * there's the possibility of getting in trouble.
-    */
-   assert(tile_x % 4 == 0);
-   assert(tile_y % 2 == 0);
-   surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
-             (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
-             (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
+   surf[5] = (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0);
 
    drm_intel_bo_emit_reloc(brw->batch.bo,
-                          brw->wm.base.surf_offset[surf_index] + 4,
-                          mt->bo,
-                          surf[1] - mt->bo->offset64,
-                          I915_GEM_DOMAIN_RENDER,
-                          I915_GEM_DOMAIN_RENDER);
+                           offset + 4,
+                           mt->bo,
+                           surf[1] - mt->bo->offset64,
+                           I915_GEM_DOMAIN_RENDER,
+                           I915_GEM_DOMAIN_RENDER);
+
+   return offset;
 }
 
 void