i965: rename legacy gs structs and functions to ff_gs.

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_urb.c

diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
index 8bb0d1b0a3bcf9f312914a783d80caf7585ef7f3..e16d30aa13a5e50744af759ddad90af662dcadcf 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -64,7 +64,7 @@ gen6_upload_urb( struct brw_context *brw )
    unsigned gs_size = vs_size;
 
    /* Calculate how many entries fit in each stage's section of the URB */
-   if (brw->gs.prog_active) {
+   if (brw->ff_gs.prog_active) {
       nr_vs_entries = (total_urb_size/2) / (vs_size * 128);
       nr_gs_entries = (total_urb_size/2) / (gs_size * 128);
    } else {
@@ -109,16 +109,16 @@ gen6_upload_urb( struct brw_context *brw )
     * doesn't exist on Gen6).  So for now we just do a full pipeline flush as
     * a workaround.
     */
-   if (brw->urb.gen6_gs_previously_active && !brw->gs.prog_active)
+   if (brw->urb.gen6_gs_previously_active && !brw->ff_gs.prog_active)
       intel_batchbuffer_emit_mi_flush(brw);
-   brw->urb.gen6_gs_previously_active = brw->gs.prog_active;
+   brw->urb.gen6_gs_previously_active = brw->ff_gs.prog_active;
 }
 
 const struct brw_tracked_state gen6_urb = {
    .dirty = {
       .mesa = 0,
       .brw = BRW_NEW_CONTEXT,
-      .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG),
+      .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_FF_GS_PROG),
    },
    .emit = gen6_upload_urb,
 };