i965: Add HiZ operation state to brw_context

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_urb.c

diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
index fc46c4cb79e3373eec99991dea33675d0c9b4bd6..d045bf28ec2222cde2ba8e1430a68671e958bea5 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -32,38 +32,40 @@
 #include "brw_defines.h"
 
 static void
-prepare_urb( struct brw_context *brw )
+gen6_upload_urb( struct brw_context *brw )
 {
-   brw->urb.nr_vs_entries = 24;
-   if (brw->gs.prog_bo)
-      brw->urb.nr_gs_entries = 4;
-   else
-      brw->urb.nr_gs_entries = 0;
+   struct intel_context *intel = &brw->intel;
+   int nr_vs_entries;
+
    /* CACHE_NEW_VS_PROG */
    brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1);
 
-   /* Check that the number of URB rows (8 floats each) allocated is less
-    * than the URB space.
-    */
-   assert((brw->urb.nr_vs_entries +
-          brw->urb.nr_gs_entries) * brw->urb.vs_size * 8 < 64 * 1024);
-}
+   /* Calculate how many VS URB entries fit in the total URB size */
+   nr_vs_entries = (brw->urb.size * 1024) / (brw->urb.vs_size * 128);
 
-static void
-upload_urb(struct brw_context *brw)
-{
-   struct intel_context *intel = &brw->intel;
+   if (nr_vs_entries > brw->urb.max_vs_entries)
+      nr_vs_entries = brw->urb.max_vs_entries;
+
+   /* According to volume 2a, nr_vs_entries must be a multiple of 4. */
+   brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 4);
+
+   /* Since we currently don't support Geometry Shaders, we always put the
+    * GS unit in passthrough mode and don't allocate it any URB space.
+    */
+   brw->urb.nr_gs_entries = 0;
+   brw->urb.gs_size = 1; /* Incorrect, but with 0 GS entries it doesn't matter. */
 
+   assert(brw->urb.nr_vs_entries >= 24);
    assert(brw->urb.nr_vs_entries % 4 == 0);
    assert(brw->urb.nr_gs_entries % 4 == 0);
    /* GS requirement */
-   assert(!brw->gs.prog_bo || brw->urb.vs_size < 5);
+   assert(!brw->gs.prog_active || brw->urb.vs_size < 5);
 
    BEGIN_BATCH(3);
    OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
    OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
             ((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT));
-   OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
+   OUT_BATCH(((brw->urb.gs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
             ((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT));
    ADVANCE_BATCH();
 }
@@ -74,6 +76,5 @@ const struct brw_tracked_state gen6_urb = {
       .brw = BRW_NEW_CONTEXT,
       .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG),
    },
-   .prepare = prepare_urb,
-   .emit = upload_urb,
+   .emit = gen6_upload_urb,
 };