i965/vec4: Make with_writemask() non-static.

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_urb.c

diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
index 2d69cbe0d395e3ae2399db9a21538715fe336395..e16d30aa13a5e50744af759ddad90af662dcadcf 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -49,12 +49,11 @@
 static void
 gen6_upload_urb( struct brw_context *brw )
 {
-   struct intel_context *intel = &brw->intel;
    int nr_vs_entries, nr_gs_entries;
    int total_urb_size = brw->urb.size * 1024; /* in bytes */
 
    /* CACHE_NEW_VS_PROG */
-   brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1);
+   unsigned vs_size = MAX2(brw->vs.prog_data->base.urb_entry_size, 1);
 
    /* We use the same VUE layout for VS outputs and GS outputs (as it's what
     * the SF and Clipper expect), so we can simply make the GS URB entry size
@@ -62,14 +61,14 @@ gen6_upload_urb( struct brw_context *brw )
     * where we have few vertex attributes and a lot of varyings, since the VS
     * size is determined by the larger of the two.  For now, it's safe.
     */
-   brw->urb.gs_size = brw->urb.vs_size;
+   unsigned gs_size = vs_size;
 
    /* Calculate how many entries fit in each stage's section of the URB */
-   if (brw->gs.prog_active) {
-      nr_vs_entries = (total_urb_size/2) / (brw->urb.vs_size * 128);
-      nr_gs_entries = (total_urb_size/2) / (brw->urb.gs_size * 128);
+   if (brw->ff_gs.prog_active) {
+      nr_vs_entries = (total_urb_size/2) / (vs_size * 128);
+      nr_gs_entries = (total_urb_size/2) / (gs_size * 128);
    } else {
-      nr_vs_entries = total_urb_size / (brw->urb.vs_size * 128);
+      nr_vs_entries = total_urb_size / (vs_size * 128);
       nr_gs_entries = 0;
    }
 
@@ -87,14 +86,14 @@ gen6_upload_urb( struct brw_context *brw )
    assert(brw->urb.nr_vs_entries >= 24);
    assert(brw->urb.nr_vs_entries % 4 == 0);
    assert(brw->urb.nr_gs_entries % 4 == 0);
-   assert(brw->urb.vs_size < 5);
-   assert(brw->urb.gs_size < 5);
+   assert(vs_size < 5);
+   assert(gs_size < 5);
 
    BEGIN_BATCH(3);
    OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
-   OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
+   OUT_BATCH(((vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
             ((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT));
-   OUT_BATCH(((brw->urb.gs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
+   OUT_BATCH(((gs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
             ((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT));
    ADVANCE_BATCH();
 
@@ -110,16 +109,16 @@ gen6_upload_urb( struct brw_context *brw )
     * doesn't exist on Gen6).  So for now we just do a full pipeline flush as
     * a workaround.
     */
-   if (brw->urb.gen6_gs_previously_active && !brw->gs.prog_active)
-      intel_batchbuffer_emit_mi_flush(intel);
-   brw->urb.gen6_gs_previously_active = brw->gs.prog_active;
+   if (brw->urb.gen6_gs_previously_active && !brw->ff_gs.prog_active)
+      intel_batchbuffer_emit_mi_flush(brw);
+   brw->urb.gen6_gs_previously_active = brw->ff_gs.prog_active;
 }
 
 const struct brw_tracked_state gen6_urb = {
    .dirty = {
       .mesa = 0,
       .brw = BRW_NEW_CONTEXT,
-      .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG),
+      .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_FF_GS_PROG),
    },
    .emit = gen6_upload_urb,
 };