i965: check tcs for NULL dereference
[mesa.git] / src / mesa / drivers / dri / i965 / gen6_vs_state.c
index 2427407c18ef59a1734ffaaca03944db41afc200..3ae00ec29c0954b7fd905aa66c29cbe1bed01077 100644 (file)
 #include "program/prog_parameter.h"
 #include "program/prog_statevars.h"
 #include "intel_batchbuffer.h"
-#include "glsl/glsl_parser_extras.h"
-
-/**
- * Creates a streamed BO containing the push constants for the VS or GS on
- * gen6+.
- *
- * Push constants are constant values (such as GLSL uniforms) that are
- * pre-loaded into a shader stage's register space at thread spawn time.
- *
- * Not all GLSL uniforms will be uploaded as push constants: The hardware has
- * a limitation of 32 or 64 EU registers (256 or 512 floats) per stage to be
- * uploaded as push constants, while GL 4.4 requires at least 1024 components
- * to be usable for the VS.  Plus, currently we always use pull constants
- * instead of push constants when doing variable-index array access.
- *
- * See brw_curbe.c for the equivalent gen4/5 code.
- */
-void
-gen6_upload_push_constants(struct brw_context *brw,
-                           const struct gl_program *prog,
-                           const struct brw_stage_prog_data *prog_data,
-                           struct brw_stage_state *stage_state,
-                           enum aub_state_struct_type type)
-{
-   struct gl_context *ctx = &brw->ctx;
-
-   /* Updates the ParamaterValues[i] pointers for all parameters of the
-    * basic type of PROGRAM_STATE_VAR.
-    */
-   /* XXX: Should this happen somewhere before to get our state flag set? */
-   _mesa_load_state_parameters(ctx, prog->Parameters);
-
-   if (prog_data->nr_params == 0) {
-      stage_state->push_const_size = 0;
-   } else {
-      gl_constant_value *param;
-      int i;
-
-      param = brw_state_batch(brw, type,
-                             prog_data->nr_params * sizeof(gl_constant_value),
-                             32, &stage_state->push_const_offset);
-
-      STATIC_ASSERT(sizeof(gl_constant_value) == sizeof(float));
-
-      /* _NEW_PROGRAM_CONSTANTS
-       *
-       * Also _NEW_TRANSFORM -- we may reference clip planes other than as a
-       * side effect of dereferencing uniforms, so _NEW_PROGRAM_CONSTANTS
-       * wouldn't be set for them.
-      */
-      for (i = 0; i < prog_data->nr_params; i++) {
-         param[i] = *prog_data->param[i];
-      }
-
-      if (0) {
-        fprintf(stderr, "%s constants:\n",
-                 _mesa_shader_stage_to_string(stage_state->stage));
-        for (i = 0; i < prog_data->nr_params; i++) {
-           if ((i & 7) == 0)
-              fprintf(stderr, "g%d: ",
-                       prog_data->dispatch_grf_start_reg + i / 8);
-           fprintf(stderr, "%8f ", param[i].f);
-           if ((i & 7) == 7)
-              fprintf(stderr, "\n");
-        }
-        if ((i & 7) != 0)
-           fprintf(stderr, "\n");
-        fprintf(stderr, "\n");
-      }
-
-      stage_state->push_const_size = ALIGN(prog_data->nr_params, 8) / 8;
-      /* We can only push 32 registers of constants at a time. */
-
-      /* From the SNB PRM (vol2, part 1, section 3.2.1.4: 3DSTATE_CONSTANT_VS:
-       *
-       *     "The sum of all four read length fields (each incremented to
-       *      represent the actual read length) must be less than or equal to
-       *      32"
-       *
-       * From the IVB PRM (vol2, part 1, section 3.2.1.3: 3DSTATE_CONSTANT_VS:
-       *
-       *     "The sum of all four read length fields must be less than or
-       *      equal to the size of 64"
-       *
-       * The other shader stages all match the VS's limits.
-       */
-      assert(stage_state->push_const_size <= 32);
-   }
-}
 
 static void
 gen6_upload_vs_push_constants(struct brw_context *brw)
@@ -130,7 +41,7 @@ gen6_upload_vs_push_constants(struct brw_context *brw)
    /* _BRW_NEW_VERTEX_PROGRAM */
    const struct brw_vertex_program *vp =
       brw_vertex_program_const(brw->vertex_program);
-   /* CACHE_NEW_VS_PROG */
+   /* BRW_NEW_VS_PROG_DATA */
    const struct brw_stage_prog_data *prog_data = &brw->vs.prog_data->base.base;
 
    gen6_upload_push_constants(brw, &vp->program.Base, prog_data,
@@ -147,11 +58,13 @@ gen6_upload_vs_push_constants(struct brw_context *brw)
 
 const struct brw_tracked_state gen6_vs_push_constants = {
    .dirty = {
-      .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
-      .brw   = (BRW_NEW_BATCH |
-                BRW_NEW_VERTEX_PROGRAM |
-                BRW_NEW_PUSH_CONSTANT_ALLOCATION),
-      .cache = CACHE_NEW_VS_PROG,
+      .mesa  = _NEW_PROGRAM_CONSTANTS |
+               _NEW_TRANSFORM,
+      .brw   = BRW_NEW_BATCH |
+               BRW_NEW_BLORP |
+               BRW_NEW_PUSH_CONSTANT_ALLOCATION |
+               BRW_NEW_VERTEX_PROGRAM |
+               BRW_NEW_VS_PROG_DATA,
    },
    .emit = gen6_upload_vs_push_constants,
 };
@@ -159,7 +72,6 @@ const struct brw_tracked_state gen6_vs_push_constants = {
 static void
 upload_vs_state(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->ctx;
    const struct brw_stage_state *stage_state = &brw->vs.base;
    uint32_t floating_point_mode = 0;
 
@@ -171,10 +83,9 @@ upload_vs_state(struct brw_context *brw)
     *   flush can be executed by sending a PIPE_CONTROL command with CS
     *   stall bit set and a post sync operation.
     *
-    * Although we don't disable the VS during normal drawing, BLORP sometimes
-    * disables it.  To be safe, do the flush here just in case.
+    * We've already done such a flush at the start of state upload, so we
+    * don't need to do another one here.
     */
-   intel_emit_post_sync_nonzero_flush(brw);
 
    if (stage_state->push_const_size == 0) {
       /* Disable the push constant buffers. */
@@ -201,10 +112,7 @@ upload_vs_state(struct brw_context *brw)
       ADVANCE_BATCH();
    }
 
-   /* Use ALT floating point mode for ARB vertex programs, because they
-    * require 0^0 == 1.
-    */
-   if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX] == NULL)
+   if (brw->vs.prog_data->base.base.use_alt_mode)
       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
 
    BEGIN_BATCH(6);
@@ -250,21 +158,22 @@ upload_vs_state(struct brw_context *brw)
     * bug reports that led to this workaround, and may be more than
     * what is strictly required to avoid the issue.
     */
-   intel_emit_post_sync_nonzero_flush(brw);
    brw_emit_pipe_control_flush(brw,
                                PIPE_CONTROL_DEPTH_STALL |
-                               PIPE_CONTROL_INSTRUCTION_FLUSH |
+                               PIPE_CONTROL_INSTRUCTION_INVALIDATE |
                                PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 }
 
 const struct brw_tracked_state gen6_vs_state = {
    .dirty = {
-      .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
-      .brw   = (BRW_NEW_CONTEXT |
-               BRW_NEW_VERTEX_PROGRAM |
-               BRW_NEW_BATCH |
-                BRW_NEW_PUSH_CONSTANT_ALLOCATION),
-      .cache = CACHE_NEW_VS_PROG
+      .mesa  = _NEW_PROGRAM_CONSTANTS |
+               _NEW_TRANSFORM,
+      .brw   = BRW_NEW_BATCH |
+               BRW_NEW_BLORP |
+               BRW_NEW_CONTEXT |
+               BRW_NEW_PUSH_CONSTANT_ALLOCATION |
+               BRW_NEW_VERTEX_PROGRAM |
+               BRW_NEW_VS_PROG_DATA,
    },
    .emit = upload_vs_state,
 };