i965: Drop the check for YUV constants in the param list.

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_vs_state.c

diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 0299dc6768c12f0d3d2073ec84360fe557ec9cd9..50047a33a87d6b2b047baaa53ef7f35cfc7dc9f8 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -29,10 +29,8 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "brw_util.h"
-#include "main/macros.h"
-#include "main/enums.h"
-#include "shader/prog_parameter.h"
-#include "shader/prog_statevars.h"
+#include "program/prog_parameter.h"
+#include "program/prog_statevars.h"
 #include "intel_batchbuffer.h"
 
 static void
@@ -46,22 +44,6 @@ upload_vs_state(struct brw_context *brw)
    drm_intel_bo *constant_bo;
    int i;
 
-   BEGIN_BATCH(6);
-   OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
-   OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-   OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
-            (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
-   OUT_BATCH(0); /* scratch space base offset */
-   OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
-            (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
-            (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
-   OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
-            GEN6_VS_STATISTICS_ENABLE|
-            GEN6_VS_ENABLE);
-   ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
-
    if (vp->use_const_buffer || nr_params == 0) {
       /* Disable the push constant buffers. */
       BEGIN_BATCH(5);
@@ -83,13 +65,13 @@ upload_vs_state(struct brw_context *brw)
       constant_bo = drm_intel_bo_alloc(intel->bufmgr, "VS constant_bo",
                                       nr_params * 4 * sizeof(float),
                                       4096);
-      intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
+      drm_intel_gem_bo_map_gtt(constant_bo);
       for (i = 0; i < nr_params; i++) {
         memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
                vp->program.Base.Parameters->ParameterValues[i],
                4 * sizeof(float));
       }
-      intel_bo_unmap_gtt_preferred(intel, constant_bo);
+      drm_intel_gem_bo_unmap_gtt(constant_bo);
 
       BEGIN_BATCH(5);
       OUT_BATCH(CMD_3D_CONSTANT_VS_STATE << 16 |
@@ -107,6 +89,22 @@ upload_vs_state(struct brw_context *brw)
    }
 
    intel_batchbuffer_emit_mi_flush(intel->batch);
+
+   BEGIN_BATCH(6);
+   OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
+   OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+   OUT_BATCH(GEN6_VS_SPF_MODE | (0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
+            (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+   OUT_BATCH(0); /* scratch space base offset */
+   OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
+            (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
+            (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
+   OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
+            GEN6_VS_STATISTICS_ENABLE |
+            GEN6_VS_ENABLE);
+   ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_vs_state = {