static void
gen6_upload_vs_push_constants(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
/* _BRW_NEW_VERTEX_PROGRAM */
const struct brw_vertex_program *vp =
brw_vertex_program_const(brw->vertex_program);
static void
upload_vs_state(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &brw->ctx;
uint32_t floating_point_mode = 0;
- /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section
+ /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
* 3DSTATE_VS, Dword 5.0 "VS Function Enable":
+ *
* [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
* command that causes the VS Function Enable to toggle. Pipeline
* flush can be executed by sending a PIPE_CONTROL command with CS
* stall bit set and a post sync operation.
+ *
+ * Although we don't disable the VS during normal drawing, BLORP sometimes
+ * disables it. To be safe, do the flush here just in case.
*/
- intel_emit_post_sync_nonzero_flush(intel);
+ intel_emit_post_sync_nonzero_flush(brw);
if (brw->vs.push_const_size == 0) {
/* Disable the push constant buffers. */
/* Use ALT floating point mode for ARB vertex programs, because they
* require 0^0 == 1.
*/
- if (intel->ctx.Shader.CurrentVertexProgram == NULL)
+ if (ctx->Shader.CurrentVertexProgram == NULL)
floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
OUT_BATCH(brw->vs.prog_offset);
OUT_BATCH(floating_point_mode |
- ((ALIGN(brw->sampler.count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT));
+ ((ALIGN(brw->vs.sampler_count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT));
if (brw->vs.prog_data->base.total_scratch) {
OUT_RELOC(brw->vs.scratch_bo,
OUT_BATCH(0);
}
- OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
+ OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg <<
+ GEN6_VS_DISPATCH_START_GRF_SHIFT) |
(brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
* bug reports that led to this workaround, and may be more than
* what is strictly required to avoid the issue.
*/
- intel_emit_post_sync_nonzero_flush(intel);
+ intel_emit_post_sync_nonzero_flush(brw);
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));