intel: Add a batch flush between front-buffer downsample and X protocol.
[mesa.git] / src / mesa / drivers / dri / i965 / gen6_vs_state.c
index da20713e93febdcf2a551539a093ed4d9a4f1031..c5f2fd03a504847d16f45b623b4d8b406ce12156 100644 (file)
@@ -149,7 +149,7 @@ upload_vs_state(struct brw_context *brw)
    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
    OUT_BATCH(brw->vs.prog_offset);
    OUT_BATCH(floating_point_mode |
-            ((ALIGN(brw->sampler.count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT));
+            ((ALIGN(brw->vs.sampler_count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT));
 
    if (brw->vs.prog_data->base.total_scratch) {
       OUT_RELOC(brw->vs.scratch_bo,
@@ -159,7 +159,8 @@ upload_vs_state(struct brw_context *brw)
       OUT_BATCH(0);
    }
 
-   OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
+   OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg <<
+              GEN6_VS_DISPATCH_START_GRF_SHIFT) |
             (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
             (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));