i965: Fix occlusion query on sandybridge

[mesa.git] / src / mesa / drivers / dri / i965 / gen6_wm_state.c

diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 58102666354bdd96da489e374b6ae8bb3c074f13..2ae0c093ebe6a07a49d7b233a48e19292b7c683d 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -29,6 +29,7 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "brw_util.h"
+#include "brw_wm.h"
 #include "program/prog_parameter.h"
 #include "program/prog_statevars.h"
 #include "intel_batchbuffer.h"
@@ -62,8 +63,24 @@ prepare_wm_constants(struct brw_context *brw)
       drm_intel_gem_bo_map_gtt(brw->wm.push_const_bo);
       constants = brw->wm.push_const_bo->virtual;
       for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
-        constants[i] = *brw->wm.prog_data->param[i];
+        constants[i] = convert_param(brw->wm.prog_data->param_convert[i],
+                                     *brw->wm.prog_data->param[i]);
       }
+
+      if (0) {
+        printf("WM constants:\n");
+        for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
+           if ((i & 7) == 0)
+              printf("g%d: ", brw->wm.prog_data->first_curbe_grf + i / 8);
+           printf("%8f ", constants[i]);
+           if ((i & 7) == 7)
+              printf("\n");
+        }
+        if ((i & 7) != 0)
+           printf("\n");
+        printf("\n");
+      }
+
       drm_intel_gem_bo_unmap_gtt(brw->wm.push_const_bo);
    }
 }
@@ -71,7 +88,7 @@ prepare_wm_constants(struct brw_context *brw)
 const struct brw_tracked_state gen6_wm_constants = {
    .dirty = {
       .mesa  = _NEW_PROGRAM_CONSTANTS,
-      .brw   = 0,
+      .brw   = BRW_NEW_FRAGMENT_PROGRAM,
       .cache = 0,
    },
    .prepare = prepare_wm_constants,
@@ -86,7 +103,8 @@ upload_wm_state(struct brw_context *brw)
       brw_fragment_program_const(brw->fragment_program);
    uint32_t dw2, dw4, dw5, dw6;
 
-   if (fp->use_const_buffer || brw->wm.prog_data->nr_params == 0) {
+   /* CACHE_NEW_WM_PROG */
+   if (brw->wm.prog_data->nr_params == 0) {
       /* Disable the push constant buffers. */
       BEGIN_BATCH(5);
       OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2));
@@ -102,21 +120,23 @@ upload_wm_state(struct brw_context *brw)
                (5 - 2));
       OUT_RELOC(brw->wm.push_const_bo,
                I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
-               ALIGN(brw->wm.prog_data->nr_params, 8) / 8 - 1);
+               ALIGN(brw->wm.prog_data->nr_params,
+                     brw->wm.prog_data->dispatch_width) / 8 - 1);
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
       ADVANCE_BATCH();
    }
 
-   intel_batchbuffer_emit_mi_flush(intel->batch);
-
    dw2 = dw4 = dw5 = dw6 = 0;
    dw4 |= GEN6_WM_STATISTICS_ENABLE;
    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 
-   /* BRW_NEW_NR_SURFACES */
+   /* OpenGL non-ieee floating point mode */
+   dw2 |= GEN6_WM_FLOATING_POINT_MODE_ALT;
+
+   /* BRW_NEW_NR_WM_SURFACES */
    dw2 |= brw->wm.nr_surfaces << GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT;
 
    /* CACHE_NEW_SAMPLER */
@@ -125,10 +145,9 @@ upload_wm_state(struct brw_context *brw)
           GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 
    dw5 |= (40 - 1) << GEN6_WM_MAX_THREADS_SHIFT;
-   dw5 |= GEN6_WM_DISPATCH_ENABLE;
 
-   /* BRW_NEW_FRAGMENT_PROGRAM */
-   if (fp->isGLSL)
+   /* CACHE_NEW_WM_PROG */
+   if (brw->wm.prog_data->dispatch_width == 8)
       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
    else
       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
@@ -151,6 +170,11 @@ upload_wm_state(struct brw_context *brw)
    if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
       dw5 |= GEN6_WM_KILL_ENABLE;
 
+   if (brw_color_buffer_write_enabled(brw) ||
+       dw5 & (GEN6_WM_KILL_ENABLE | GEN6_WM_COMPUTED_DEPTH)) {
+      dw5 |= GEN6_WM_DISPATCH_ENABLE;
+   }
+
    dw6 |= GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
 
    dw6 |= brw_count_bits(brw->fragment_program->Base.InputsRead) <<
@@ -167,20 +191,19 @@ upload_wm_state(struct brw_context *brw)
    OUT_BATCH(0); /* kernel 1 pointer */
    OUT_BATCH(0); /* kernel 2 pointer */
    ADVANCE_BATCH();
-
-   intel_batchbuffer_emit_mi_flush(intel->batch);
 }
 
 const struct brw_tracked_state gen6_wm_state = {
    .dirty = {
-      .mesa  = (_NEW_LINE | _NEW_POLYGONSTIPPLE | _NEW_COLOR |
-               _NEW_PROGRAM_CONSTANTS),
+      .mesa  = (_NEW_LINE | _NEW_POLYGONSTIPPLE | _NEW_COLOR | _NEW_BUFFERS |
+               _NEW_PROGRAM_CONSTANTS | _NEW_POLYGON),
       .brw   = (BRW_NEW_CURBE_OFFSETS |
                BRW_NEW_FRAGMENT_PROGRAM |
                 BRW_NEW_NR_WM_SURFACES |
                BRW_NEW_URB_FENCE |
                BRW_NEW_BATCH),
-      .cache = CACHE_NEW_SAMPLER
+      .cache = (CACHE_NEW_SAMPLER |
+               CACHE_NEW_WM_PROG)
    },
    .emit = upload_wm_state,
 };