gen7_blorp_emit_urb_config(struct brw_context *brw,
const brw_blorp_params *params)
{
- /* The minimum valid value is 32. See 3DSTATE_URB_VS,
- * Dword 1.15:0 "VS Number of URB Entries".
+ unsigned urb_size = (brw->is_haswell && brw->gt == 3) ? 32 : 16;
+ gen7_emit_push_constant_state(brw,
+ urb_size / 2 /* vs_size */,
+ 0 /* gs_size */,
+ urb_size / 2 /* fs_size */);
+
+ /* The minimum valid number of VS entries is 32. See 3DSTATE_URB_VS, Dword
+ * 1.15:0 "VS Number of URB Entries".
*/
- int num_vs_entries = 32;
- int vs_size = 2;
- int vs_start = 2; /* skip over push constants */
-
- gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start);
+ gen7_emit_urb_state(brw,
+ 32 /* num_vs_entries */,
+ 2 /* vs_size */,
+ 2 /* vs_start */,
+ 0 /* num_gs_entries */,
+ 1 /* gs_size */,
+ 2 /* gs_start */);
}
*/
struct intel_region *region = surface->mt->region;
uint32_t tile_x, tile_y;
- uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+ const uint8_t mocs = GEN7_MOCS_L3;
uint32_t tiling = surface->map_stencil_as_y_tiled
? I915_TILING_Y : region->tiling;
/* reloc */
surf[1] =
- surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset;
+ surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset64;
/* Note that the low bits of these fields are missing, so
* there's the possibility of getting in trouble.
drm_intel_bo_emit_reloc(brw->batch.bo,
wm_surf_offset + 4,
region->bo,
- surf[1] - region->bo->offset,
+ surf[1] - region->bo->offset64,
read_domains, write_domain);
gen7_check_surface_setup(surf, is_render_target);
// sampler->ss0.min_mag_neq = 1;
- /* Set LOD bias:
+ /* Set LOD bias:
*/
sampler->ss0.lod_bias = 0;
sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
- /* Set BaseMipLevel, MaxLOD, MinLOD:
+ /* Set BaseMipLevel, MaxLOD, MinLOD:
*
* XXX: I don't think that using firstLevel, lastLevel works,
* because we always setup the surface state as if firstLevel ==
OUT_BATCH(0);
ADVANCE_BATCH();
+ /**
+ * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
+ * Geometry > Geometry Shader > State:
+ *
+ * "Note: Because of corruption in IVB:GT2, software needs to flush the
+ * whole fixed function pipeline when the GS enable changes value in
+ * the 3DSTATE_GS."
+ *
+ * The hardware architects have clarified that in this context "flush the
+ * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
+ * Stall" bit set.
+ */
+ if (!brw->is_haswell && brw->gt == 2 && brw->gs.enabled)
+ gen7_emit_cs_stall_flush(brw);
+
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
+ brw->gs.enabled = false;
}
/* 3DSTATE_STREAMOUT
OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
OUT_BATCH(params->depth_format <<
GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
- OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
+ OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
}
- if (params->num_samples > 1) {
+ if (params->dst.num_samples > 1) {
dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
if (prog_data && prog_data->persample_msaa_dispatch)
dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
const brw_blorp_params *params,
uint32_t wm_push_const_offset)
{
- uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+ const uint8_t mocs = GEN7_MOCS_L3;
/* Make sure the push constants fill an exact integer number of
* registers.
gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
const brw_blorp_params *params)
{
- uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+ const uint8_t mocs = GEN7_MOCS_L3;
uint32_t surfwidth, surfheight;
uint32_t surftype;
unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
surfwidth = params->depth.width;
surfheight = params->depth.height;
} else {
- surfwidth = params->depth.mt->physical_width0;
- surfheight = params->depth.mt->physical_height0;
+ surfwidth = params->depth.mt->logical_width0;
+ surfheight = params->depth.mt->logical_height0;
}
/* 3DSTATE_DEPTH_BUFFER */
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
+
+ BEGIN_BATCH(3);
+ OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+
+ BEGIN_BATCH(3);
+ OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
}
gen7_blorp_exec(struct brw_context *brw,
const brw_blorp_params *params)
{
+ if (brw->gen >= 8)
+ return;
+
brw_blorp_prog_data *prog_data = NULL;
uint32_t cc_blend_state_offset = 0;
uint32_t cc_state_offset = 0;
uint32_t sampler_offset = 0;
uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
- gen6_blorp_emit_batch_head(brw, params);
- gen6_emit_3dstate_multisample(brw, params->num_samples);
- gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false, ~0u);
+ gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
+ gen6_emit_3dstate_sample_mask(brw,
+ params->dst.num_samples > 1 ?
+ (1 << params->dst.num_samples) - 1 : 1);
gen6_blorp_emit_state_base_address(brw, params);
gen6_blorp_emit_vertices(brw, params);
gen7_blorp_emit_urb_config(brw, params);
projects / mesa.git / blobdiff