i965/nir/vec4: Prepare source and destination registers for ALU operations

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_blorp.cpp

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index c9e7cb7f04967be2d4a5e56ecbc2326df2594302..9822dc1fe7980ddd44a375589fe35d6d9c6b7a8b 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -415,9 +415,11 @@ gen7_blorp_emit_sf_config(struct brw_context *brw,
    {
       BEGIN_BATCH(14);
       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
-      OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
+      OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
+                params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
-                0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
+                BRW_SF_URB_ENTRY_READ_OFFSET <<
+                   GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
       for (int i = 0; i < 12; ++i)
          OUT_BATCH(0);
       ADVANCE_BATCH();
@@ -643,7 +645,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    /* 3DSTATE_DEPTH_BUFFER */
    {
-      intel_emit_depth_stall_flushes(brw);
+      brw_emit_depth_stall_flushes(brw);
 
       BEGIN_BATCH(7);
       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
@@ -694,7 +696,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 static void
 gen7_blorp_emit_depth_disable(struct brw_context *brw)
 {
-   intel_emit_depth_stall_flushes(brw);
+   brw_emit_depth_stall_flushes(brw);
 
    BEGIN_BATCH(7);
    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
@@ -751,7 +753,7 @@ gen7_blorp_emit_primitive(struct brw_context *brw,
              _3DPRIM_RECTLIST);
    OUT_BATCH(3); /* vertex count per instance */
    OUT_BATCH(0);
-   OUT_BATCH(1); /* instance count */
+   OUT_BATCH(params->num_layers); /* instance count */
    OUT_BATCH(0);
    OUT_BATCH(0);
    ADVANCE_BATCH();
@@ -786,12 +788,14 @@ gen7_blorp_exec(struct brw_context *brw,
    gen7_blorp_emit_urb_config(brw);
    if (params->use_wm_prog) {
       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
-      cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
+      cc_state_offset = gen6_blorp_emit_cc_state(brw);
       gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
       gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
    }
    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
    gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
+   if (brw->use_resource_streamer)
+      gen7_disable_hw_binding_tables(brw);
    if (params->use_wm_prog) {
       uint32_t wm_surf_offset_renderbuffer;
       uint32_t wm_surf_offset_texture = 0;
@@ -809,7 +813,7 @@ gen7_blorp_exec(struct brw_context *brw,
                                           false /* is_render_target */);
       }
       wm_bind_bo_offset =
-         gen6_blorp_emit_binding_table(brw, params,
+         gen6_blorp_emit_binding_table(brw,
                                        wm_surf_offset_renderbuffer,
                                        wm_surf_offset_texture);
       sampler_offset =
@@ -821,7 +825,7 @@ gen7_blorp_exec(struct brw_context *brw,
    gen7_blorp_emit_ds_disable(brw);
    gen7_blorp_emit_gs_disable(brw);
    gen7_blorp_emit_streamout_disable(brw);
-   gen6_blorp_emit_clip_disable(brw, params);
+   gen6_blorp_emit_clip_disable(brw);
    gen7_blorp_emit_sf_config(brw, params);
    gen7_blorp_emit_wm_config(brw, params, prog_data);
    if (params->use_wm_prog) {