*/
struct intel_region *region = surface->mt->region;
uint32_t tile_x, tile_y;
- uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+ const uint8_t mocs = GEN7_MOCS_L3;
uint32_t tiling = surface->map_stencil_as_y_tiled
? I915_TILING_Y : region->tiling;
const brw_blorp_params *params,
uint32_t wm_push_const_offset)
{
- uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+ const uint8_t mocs = GEN7_MOCS_L3;
/* Make sure the push constants fill an exact integer number of
* registers.
gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
const brw_blorp_params *params)
{
- uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+ const uint8_t mocs = GEN7_MOCS_L3;
uint32_t surfwidth, surfheight;
uint32_t surftype;
unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
gen7_blorp_emit_depth_disable(struct brw_context *brw,
const brw_blorp_params *params)
{
+ intel_emit_depth_stall_flushes(brw);
+
BEGIN_BATCH(7);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));