i965/miptree: Rename align_w,align_h -> halign,valign

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_blorp.cpp

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 1cf55fd4cf586504d063d6b9d1d4bf6e809c1298..f90e78e43c739a1c68a9da64c1e97b292759b1f2 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -48,8 +48,7 @@
  *     valid.
  */
 static void
-gen7_blorp_emit_urb_config(struct brw_context *brw,
-                           const brw_blorp_params *params)
+gen7_blorp_emit_urb_config(struct brw_context *brw)
 {
    unsigned urb_size = (brw->is_haswell && brw->gt == 3) ? 32 : 16;
    gen7_emit_push_constant_state(brw,
@@ -73,7 +72,6 @@ gen7_blorp_emit_urb_config(struct brw_context *brw,
 /* 3DSTATE_BLEND_STATE_POINTERS */
 static void
 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
-                                    const brw_blorp_params *params,
                                     uint32_t cc_blend_state_offset)
 {
    BEGIN_BATCH(2);
@@ -86,7 +84,6 @@ gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
 /* 3DSTATE_CC_STATE_POINTERS */
 static void
 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
-                                 const brw_blorp_params *params,
                                  uint32_t cc_state_offset)
 {
    BEGIN_BATCH(2);
@@ -96,8 +93,7 @@ gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
 }
 
 static void
-gen7_blorp_emit_cc_viewport(struct brw_context *brw,
-                           const brw_blorp_params *params)
+gen7_blorp_emit_cc_viewport(struct brw_context *brw)
 {
    struct brw_cc_viewport *ccv;
    uint32_t cc_vp_offset;
@@ -121,7 +117,6 @@ gen7_blorp_emit_cc_viewport(struct brw_context *brw,
  */
 static void
 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
-                                             const brw_blorp_params *params,
                                              uint32_t depthstencil_offset)
 {
    BEGIN_BATCH(2);
@@ -136,7 +131,6 @@ gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
  */
 static uint32_t
 gen7_blorp_emit_surface_state(struct brw_context *brw,
-                              const brw_blorp_params *params,
                               const brw_blorp_surface_info *surface,
                               uint32_t read_domains, uint32_t write_domain,
                               bool is_render_target)
@@ -164,12 +158,12 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
              gen7_surface_tiling_mode(tiling);
 
-   if (surface->mt->align_h == 4)
+   if (surface->mt->valign == 4)
       surf[0] |= GEN7_SURFACE_VALIGN_4;
-   if (surface->mt->align_w == 8)
+   if (surface->mt->halign == 8)
       surf[0] |= GEN7_SURFACE_HALIGN_8;
 
-   if (surface->array_spacing_lod0)
+   if (surface->array_layout == ALL_SLICES_AT_EACH_LOD)
       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
    else
       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
@@ -228,8 +222,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
  * Disable vertex shader.
  */
 static void
-gen7_blorp_emit_vs_disable(struct brw_context *brw,
-                           const brw_blorp_params *params)
+gen7_blorp_emit_vs_disable(struct brw_context *brw)
 {
    BEGIN_BATCH(7);
    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
@@ -257,8 +250,7 @@ gen7_blorp_emit_vs_disable(struct brw_context *brw,
  * Disable the hull shader.
  */
 static void
-gen7_blorp_emit_hs_disable(struct brw_context *brw,
-                           const brw_blorp_params *params)
+gen7_blorp_emit_hs_disable(struct brw_context *brw)
 {
    BEGIN_BATCH(7);
    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
@@ -287,8 +279,7 @@ gen7_blorp_emit_hs_disable(struct brw_context *brw,
  * Disable the tesselation engine.
  */
 static void
-gen7_blorp_emit_te_disable(struct brw_context *brw,
-                           const brw_blorp_params *params)
+gen7_blorp_emit_te_disable(struct brw_context *brw)
 {
    BEGIN_BATCH(4);
    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
@@ -304,8 +295,7 @@ gen7_blorp_emit_te_disable(struct brw_context *brw,
  * Disable the domain shader.
  */
 static void
-gen7_blorp_emit_ds_disable(struct brw_context *brw,
-                           const brw_blorp_params *params)
+gen7_blorp_emit_ds_disable(struct brw_context *brw)
 {
    BEGIN_BATCH(7);
    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
@@ -332,8 +322,7 @@ gen7_blorp_emit_ds_disable(struct brw_context *brw,
  * Disable the geometry shader.
  */
 static void
-gen7_blorp_emit_gs_disable(struct brw_context *brw,
-                           const brw_blorp_params *params)
+gen7_blorp_emit_gs_disable(struct brw_context *brw)
 {
    BEGIN_BATCH(7);
    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
@@ -377,8 +366,7 @@ gen7_blorp_emit_gs_disable(struct brw_context *brw,
  * Disable streamout.
  */
 static void
-gen7_blorp_emit_streamout_disable(struct brw_context *brw,
-                                  const brw_blorp_params *params)
+gen7_blorp_emit_streamout_disable(struct brw_context *brw)
 {
    BEGIN_BATCH(3);
    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
@@ -427,9 +415,11 @@ gen7_blorp_emit_sf_config(struct brw_context *brw,
    {
       BEGIN_BATCH(14);
       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
-      OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
+      OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
+                params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
-                0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
+                BRW_SF_URB_ENTRY_READ_OFFSET <<
+                   GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
       for (int i = 0; i < 12; ++i)
          OUT_BATCH(0);
       ADVANCE_BATCH();
@@ -529,17 +519,6 @@ gen7_blorp_emit_ps_config(struct brw_context *brw,
       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
    }
 
-   switch (params->fast_clear_op) {
-   case GEN7_FAST_CLEAR_OP_FAST_CLEAR:
-      dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
-      break;
-   case GEN7_FAST_CLEAR_OP_RESOLVE:
-      dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE;
-      break;
-   default:
-      break;
-   }
-
    BEGIN_BATCH(8);
    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
@@ -555,7 +534,6 @@ gen7_blorp_emit_ps_config(struct brw_context *brw,
 
 static void
 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
-                                          const brw_blorp_params *params,
                                           uint32_t wm_bind_bo_offset)
 {
    BEGIN_BATCH(2);
@@ -567,7 +545,6 @@ gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 
 static void
 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
-                                          const brw_blorp_params *params,
                                           uint32_t sampler_offset)
 {
    BEGIN_BATCH(2);
@@ -579,7 +556,6 @@ gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 
 static void
 gen7_blorp_emit_constant_ps(struct brw_context *brw,
-                            const brw_blorp_params *params,
                             uint32_t wm_push_const_offset)
 {
    const uint8_t mocs = GEN7_MOCS_L3;
@@ -606,8 +582,7 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw,
 }
 
 static void
-gen7_blorp_emit_constant_ps_disable(struct brw_context *brw,
-                                    const brw_blorp_params *params)
+gen7_blorp_emit_constant_ps_disable(struct brw_context *brw)
 {
    BEGIN_BATCH(7);
    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
@@ -670,7 +645,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    /* 3DSTATE_DEPTH_BUFFER */
    {
-      intel_emit_depth_stall_flushes(brw);
+      brw_emit_depth_stall_flushes(brw);
 
       BEGIN_BATCH(7);
       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
@@ -695,13 +670,13 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    /* 3DSTATE_HIER_DEPTH_BUFFER */
    {
-      struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_mt;
+      struct intel_miptree_aux_buffer *hiz_buf = params->depth.mt->hiz_buf;
 
       BEGIN_BATCH(3);
       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
       OUT_BATCH((mocs << 25) |
-                (hiz_mt->pitch - 1));
-      OUT_RELOC(hiz_mt->bo,
+                (hiz_buf->pitch - 1));
+      OUT_RELOC(hiz_buf->bo,
                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                 0);
       ADVANCE_BATCH();
@@ -719,10 +694,9 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
 
 static void
-gen7_blorp_emit_depth_disable(struct brw_context *brw,
-                              const brw_blorp_params *params)
+gen7_blorp_emit_depth_disable(struct brw_context *brw)
 {
-   intel_emit_depth_stall_flushes(brw);
+   brw_emit_depth_stall_flushes(brw);
 
    BEGIN_BATCH(7);
    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
@@ -779,7 +753,7 @@ gen7_blorp_emit_primitive(struct brw_context *brw,
              _3DPRIM_RECTLIST);
    OUT_BATCH(3); /* vertex count per instance */
    OUT_BATCH(0);
-   OUT_BATCH(1); /* instance count */
+   OUT_BATCH(params->num_layers); /* instance count */
    OUT_BATCH(0);
    OUT_BATCH(0);
    ADVANCE_BATCH();
@@ -811,62 +785,63 @@ gen7_blorp_exec(struct brw_context *brw,
                                  (1 << params->dst.num_samples) - 1 : 1);
    gen6_blorp_emit_state_base_address(brw, params);
    gen6_blorp_emit_vertices(brw, params);
-   gen7_blorp_emit_urb_config(brw, params);
+   gen7_blorp_emit_urb_config(brw);
    if (params->use_wm_prog) {
       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
-      cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
-      gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
-      gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
+      cc_state_offset = gen6_blorp_emit_cc_state(brw);
+      gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
+      gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
    }
    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
-   gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
-                                                depthstencil_offset);
+   gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
+   if (brw->use_resource_streamer)
+      gen7_disable_hw_binding_tables(brw);
    if (params->use_wm_prog) {
       uint32_t wm_surf_offset_renderbuffer;
       uint32_t wm_surf_offset_texture = 0;
       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
       intel_miptree_used_for_rendering(params->dst.mt);
       wm_surf_offset_renderbuffer =
-         gen7_blorp_emit_surface_state(brw, params, &params->dst,
+         gen7_blorp_emit_surface_state(brw, &params->dst,
                                        I915_GEM_DOMAIN_RENDER,
                                        I915_GEM_DOMAIN_RENDER,
                                        true /* is_render_target */);
       if (params->src.mt) {
          wm_surf_offset_texture =
-            gen7_blorp_emit_surface_state(brw, params, &params->src,
+            gen7_blorp_emit_surface_state(brw, &params->src,
                                           I915_GEM_DOMAIN_SAMPLER, 0,
                                           false /* is_render_target */);
       }
       wm_bind_bo_offset =
-         gen6_blorp_emit_binding_table(brw, params,
+         gen6_blorp_emit_binding_table(brw,
                                        wm_surf_offset_renderbuffer,
                                        wm_surf_offset_texture);
-      sampler_offset = gen6_blorp_emit_sampler_state(brw, params);
+      sampler_offset =
+         gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
    }
-   gen7_blorp_emit_vs_disable(brw, params);
-   gen7_blorp_emit_hs_disable(brw, params);
-   gen7_blorp_emit_te_disable(brw, params);
-   gen7_blorp_emit_ds_disable(brw, params);
-   gen7_blorp_emit_gs_disable(brw, params);
-   gen7_blorp_emit_streamout_disable(brw, params);
-   gen6_blorp_emit_clip_disable(brw, params);
+   gen7_blorp_emit_vs_disable(brw);
+   gen7_blorp_emit_hs_disable(brw);
+   gen7_blorp_emit_te_disable(brw);
+   gen7_blorp_emit_ds_disable(brw);
+   gen7_blorp_emit_gs_disable(brw);
+   gen7_blorp_emit_streamout_disable(brw);
+   gen6_blorp_emit_clip_disable(brw);
    gen7_blorp_emit_sf_config(brw, params);
    gen7_blorp_emit_wm_config(brw, params, prog_data);
    if (params->use_wm_prog) {
-      gen7_blorp_emit_binding_table_pointers_ps(brw, params,
-                                                wm_bind_bo_offset);
-      gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
-      gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
+      gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
+      gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
+      gen7_blorp_emit_constant_ps(brw, wm_push_const_offset);
    } else {
-      gen7_blorp_emit_constant_ps_disable(brw, params);
+      gen7_blorp_emit_constant_ps_disable(brw);
    }
    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
-   gen7_blorp_emit_cc_viewport(brw, params);
+   gen7_blorp_emit_cc_viewport(brw);
 
    if (params->depth.mt)
       gen7_blorp_emit_depth_stencil_config(brw, params);
    else
-      gen7_blorp_emit_depth_disable(brw, params);
+      gen7_blorp_emit_depth_disable(brw);
    gen7_blorp_emit_clear_params(brw, params);
    gen6_blorp_emit_drawing_rectangle(brw, params);
    gen7_blorp_emit_primitive(brw, params);