* valid.
*/
static void
-gen7_blorp_emit_urb_config(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_urb_config(struct brw_context *brw)
{
unsigned urb_size = (brw->is_haswell && brw->gt == 3) ? 32 : 16;
gen7_emit_push_constant_state(brw,
/* 3DSTATE_BLEND_STATE_POINTERS */
static void
gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t cc_blend_state_offset)
{
BEGIN_BATCH(2);
/* 3DSTATE_CC_STATE_POINTERS */
static void
gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t cc_state_offset)
{
BEGIN_BATCH(2);
}
static void
-gen7_blorp_emit_cc_viewport(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_cc_viewport(struct brw_context *brw)
{
struct brw_cc_viewport *ccv;
uint32_t cc_vp_offset;
*/
static void
gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t depthstencil_offset)
{
BEGIN_BATCH(2);
*/
static uint32_t
gen7_blorp_emit_surface_state(struct brw_context *brw,
- const brw_blorp_params *params,
const brw_blorp_surface_info *surface,
uint32_t read_domains, uint32_t write_domain,
bool is_render_target)
* to divide them by 2 as we do for Gen6 (see
* gen6_blorp_emit_surface_state).
*/
- struct intel_region *region = surface->mt->region;
+ struct intel_mipmap_tree *mt = surface->mt;
uint32_t tile_x, tile_y;
const uint8_t mocs = GEN7_MOCS_L3;
uint32_t tiling = surface->map_stencil_as_y_tiled
- ? I915_TILING_Y : region->tiling;
+ ? I915_TILING_Y : mt->tiling;
uint32_t *surf = (uint32_t *)
brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
gen7_surface_tiling_mode(tiling);
- if (surface->mt->align_h == 4)
+ if (surface->mt->valign == 4)
surf[0] |= GEN7_SURFACE_VALIGN_4;
- if (surface->mt->align_w == 8)
+ if (surface->mt->halign == 8)
surf[0] |= GEN7_SURFACE_HALIGN_8;
- if (surface->array_spacing_lod0)
+ if (surface->array_layout == ALL_SLICES_AT_EACH_LOD)
surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
else
surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
/* reloc */
surf[1] =
- surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset;
+ surface->compute_tile_offsets(&tile_x, &tile_y) + mt->bo->offset64;
/* Note that the low bits of these fields are missing, so
* there's the possibility of getting in trouble.
surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
- uint32_t pitch_bytes = region->pitch;
+ uint32_t pitch_bytes = mt->pitch;
if (surface->map_stencil_as_y_tiled)
pitch_bytes *= 2;
surf[3] = pitch_bytes - 1;
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->batch.bo,
wm_surf_offset + 4,
- region->bo,
- surf[1] - region->bo->offset,
+ mt->bo,
+ surf[1] - mt->bo->offset64,
read_domains, write_domain);
gen7_check_surface_setup(surf, is_render_target);
}
-/**
- * SAMPLER_STATE. See gen7_update_sampler_state().
- */
-static uint32_t
-gen7_blorp_emit_sampler_state(struct brw_context *brw,
- const brw_blorp_params *params)
-{
- uint32_t sampler_offset;
-
- struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
- brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
- sizeof(struct gen7_sampler_state),
- 32, &sampler_offset);
- memset(sampler, 0, sizeof(*sampler));
-
- sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
- sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
- sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
-
- sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
- sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
- sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
-
- // sampler->ss0.min_mag_neq = 1;
-
- /* Set LOD bias:
- */
- sampler->ss0.lod_bias = 0;
-
- sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
- sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
-
- /* Set BaseMipLevel, MaxLOD, MinLOD:
- *
- * XXX: I don't think that using firstLevel, lastLevel works,
- * because we always setup the surface state as if firstLevel ==
- * level zero. Probably have to subtract firstLevel from each of
- * these:
- */
- sampler->ss0.base_level = U_FIXED(0, 1);
-
- sampler->ss1.max_lod = U_FIXED(0, 8);
- sampler->ss1.min_lod = U_FIXED(0, 8);
-
- sampler->ss3.non_normalized_coord = 1;
-
- sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
- BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
- BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
- sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
- BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
- BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
-
- return sampler_offset;
-}
-
-
/* 3DSTATE_VS
*
* Disable vertex shader.
*/
static void
-gen7_blorp_emit_vs_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_vs_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
* Disable the hull shader.
*/
static void
-gen7_blorp_emit_hs_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_hs_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
* Disable the tesselation engine.
*/
static void
-gen7_blorp_emit_te_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_te_disable(struct brw_context *brw)
{
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
* Disable the domain shader.
*/
static void
-gen7_blorp_emit_ds_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_ds_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
* Disable the geometry shader.
*/
static void
-gen7_blorp_emit_gs_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_gs_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
* Disable streamout.
*/
static void
-gen7_blorp_emit_streamout_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_streamout_disable(struct brw_context *brw)
{
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
{
BEGIN_BATCH(14);
OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
- OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
+ OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
+ params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
- 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
+ BRW_SF_URB_ENTRY_READ_OFFSET <<
+ GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
for (int i = 0; i < 12; ++i)
OUT_BATCH(0);
ADVANCE_BATCH();
case GEN6_HIZ_OP_NONE:
break;
default:
- assert(0);
- break;
+ unreachable("not reached");
}
dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
}
- switch (params->fast_clear_op) {
- case GEN7_FAST_CLEAR_OP_FAST_CLEAR:
- dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
- break;
- case GEN7_FAST_CLEAR_OP_RESOLVE:
- dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE;
- break;
- default:
- break;
- }
-
BEGIN_BATCH(8);
OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
static void
gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t wm_bind_bo_offset)
{
BEGIN_BATCH(2);
static void
gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t sampler_offset)
{
BEGIN_BATCH(2);
static void
gen7_blorp_emit_constant_ps(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t wm_push_const_offset)
{
const uint8_t mocs = GEN7_MOCS_L3;
}
static void
-gen7_blorp_emit_constant_ps_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_constant_ps_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
/* 3DSTATE_DEPTH_BUFFER */
{
- intel_emit_depth_stall_flushes(brw);
+ brw_emit_depth_stall_flushes(brw);
BEGIN_BATCH(7);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
- OUT_BATCH((params->depth.mt->region->pitch - 1) |
+ OUT_BATCH((params->depth.mt->pitch - 1) |
params->depth_format << 18 |
1 << 22 | /* hiz enable */
1 << 28 | /* depth write */
surftype << 29);
- OUT_RELOC(params->depth.mt->region->bo,
+ OUT_RELOC(params->depth.mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_BATCH((surfwidth - 1) << 4 |
/* 3DSTATE_HIER_DEPTH_BUFFER */
{
- struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
+ struct intel_miptree_aux_buffer *hiz_buf = params->depth.mt->hiz_buf;
BEGIN_BATCH(3);
OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH((mocs << 25) |
- (hiz_region->pitch - 1));
- OUT_RELOC(hiz_region->bo,
+ (hiz_buf->pitch - 1));
+ OUT_RELOC(hiz_buf->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
ADVANCE_BATCH();
static void
-gen7_blorp_emit_depth_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_depth_disable(struct brw_context *brw)
{
- intel_emit_depth_stall_flushes(brw);
+ brw_emit_depth_stall_flushes(brw);
BEGIN_BATCH(7);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
_3DPRIM_RECTLIST);
OUT_BATCH(3); /* vertex count per instance */
OUT_BATCH(0);
- OUT_BATCH(1); /* instance count */
+ OUT_BATCH(params->num_layers); /* instance count */
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
(1 << params->dst.num_samples) - 1 : 1);
gen6_blorp_emit_state_base_address(brw, params);
gen6_blorp_emit_vertices(brw, params);
- gen7_blorp_emit_urb_config(brw, params);
+ gen7_blorp_emit_urb_config(brw);
if (params->use_wm_prog) {
cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
- cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
- gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
- gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
+ cc_state_offset = gen6_blorp_emit_cc_state(brw);
+ gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
+ gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
}
depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
- gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
- depthstencil_offset);
+ gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
+ if (brw->use_resource_streamer)
+ gen7_disable_hw_binding_tables(brw);
if (params->use_wm_prog) {
uint32_t wm_surf_offset_renderbuffer;
uint32_t wm_surf_offset_texture = 0;
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
intel_miptree_used_for_rendering(params->dst.mt);
wm_surf_offset_renderbuffer =
- gen7_blorp_emit_surface_state(brw, params, ¶ms->dst,
+ gen7_blorp_emit_surface_state(brw, ¶ms->dst,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER,
true /* is_render_target */);
if (params->src.mt) {
wm_surf_offset_texture =
- gen7_blorp_emit_surface_state(brw, params, ¶ms->src,
+ gen7_blorp_emit_surface_state(brw, ¶ms->src,
I915_GEM_DOMAIN_SAMPLER, 0,
false /* is_render_target */);
}
wm_bind_bo_offset =
- gen6_blorp_emit_binding_table(brw, params,
+ gen6_blorp_emit_binding_table(brw,
wm_surf_offset_renderbuffer,
wm_surf_offset_texture);
- sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
+ sampler_offset =
+ gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
}
- gen7_blorp_emit_vs_disable(brw, params);
- gen7_blorp_emit_hs_disable(brw, params);
- gen7_blorp_emit_te_disable(brw, params);
- gen7_blorp_emit_ds_disable(brw, params);
- gen7_blorp_emit_gs_disable(brw, params);
- gen7_blorp_emit_streamout_disable(brw, params);
- gen6_blorp_emit_clip_disable(brw, params);
+ gen7_blorp_emit_vs_disable(brw);
+ gen7_blorp_emit_hs_disable(brw);
+ gen7_blorp_emit_te_disable(brw);
+ gen7_blorp_emit_ds_disable(brw);
+ gen7_blorp_emit_gs_disable(brw);
+ gen7_blorp_emit_streamout_disable(brw);
+ gen6_blorp_emit_clip_disable(brw);
gen7_blorp_emit_sf_config(brw, params);
gen7_blorp_emit_wm_config(brw, params, prog_data);
if (params->use_wm_prog) {
- gen7_blorp_emit_binding_table_pointers_ps(brw, params,
- wm_bind_bo_offset);
- gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
- gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
+ gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
+ gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
+ gen7_blorp_emit_constant_ps(brw, wm_push_const_offset);
} else {
- gen7_blorp_emit_constant_ps_disable(brw, params);
+ gen7_blorp_emit_constant_ps_disable(brw);
}
gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
- gen7_blorp_emit_cc_viewport(brw, params);
+ gen7_blorp_emit_cc_viewport(brw);
if (params->depth.mt)
gen7_blorp_emit_depth_stencil_config(brw, params);
else
- gen7_blorp_emit_depth_disable(brw, params);
+ gen7_blorp_emit_depth_disable(brw);
gen7_blorp_emit_clear_params(brw, params);
gen6_blorp_emit_drawing_rectangle(brw, params);
gen7_blorp_emit_primitive(brw, params);
projects / mesa.git / blobdiff