i965/vec4: Don't lose the force_writemask_all flag during CSE.
[mesa.git] / src / mesa / drivers / dri / i965 / gen7_disable.c
index c152d0accaa44c4324b31c37e6b5efd0a04e9992..2c43cd77f07e13146947f60b28085dfabfb95ea2 100644 (file)
 #include "brw_defines.h"
 #include "intel_batchbuffer.h"
 
-void
-gen7_disable_unused_stages(struct brw_context *brw)
+static void
+disable_stages(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-
-   assert(!brw->gs.prog_active);
-
-   /* Disable the Geometry Shader (GS) Unit */
-   BEGIN_BATCH(7);
-   OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-
-   BEGIN_BATCH(7);
-   OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
-   OUT_BATCH(0); /* prog_bo */
-   OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
-            (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
-   OUT_BATCH(0); /* scratch space base offset */
-   OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
-            (0 << GEN6_GS_URB_READ_LENGTH_SHIFT) |
-            GEN7_GS_INCLUDE_VERTEX_HANDLES |
-            (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
-   OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
-            GEN6_GS_STATISTICS_ENABLE);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-
-   BEGIN_BATCH(2);
-   OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_GS << 16 | (2 - 2));
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-
    /* Disable the HS Unit */
    BEGIN_BATCH(7);
    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
@@ -123,3 +88,11 @@ gen7_disable_unused_stages(struct brw_context *brw)
    OUT_BATCH(0);
    ADVANCE_BATCH();
 }
+
+const struct brw_tracked_state gen7_disable_stages = {
+   .dirty = {
+      .mesa  = 0,
+      .brw   = BRW_NEW_CONTEXT,
+   },
+   .emit = disable_stages,
+};