i965: Update max VS/PS threads shift offsets for Haswell.

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_hiz.c

diff --git a/src/mesa/drivers/dri/i965/gen7_hiz.c b/src/mesa/drivers/dri/i965/gen7_hiz.c
index 50c265ece9b7ce61376f2fdac62ccbe53f312f25..18c178eb04148a055be4b133897fa3a8201c5f70 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_hiz.c
+++ b/src/mesa/drivers/dri/i965/gen7_hiz.c
@@ -314,7 +314,7 @@ gen7_hiz_exec(struct intel_context *intel,
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
-      OUT_BATCH(((brw->max_wm_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT) |
+      OUT_BATCH(((brw->max_wm_threads - 1) << IVB_PS_MAX_THREADS_SHIFT) |
                GEN7_PS_32_DISPATCH_ENABLE);
       OUT_BATCH(0);
       OUT_BATCH(0);