i965/eu: Take into account the target cache argument in brw_set_dp_read_message.
[mesa.git] / src / mesa / drivers / dri / i965 / gen7_hs_state.c
index 0e2b3b2604e45d0f57d602e885ce7d57a194b8fa..7cde0300710037c4a6ddc7ca58ded0e9fb03394e 100644 (file)
@@ -25,6 +25,7 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "intel_batchbuffer.h"
+#include "main/shaderapi.h"
 
 static void
 gen7_upload_tcs_push_constants(struct brw_context *brw)
@@ -38,6 +39,8 @@ gen7_upload_tcs_push_constants(struct brw_context *brw)
    if (active) {
       /* BRW_NEW_TCS_PROG_DATA */
       const struct brw_stage_prog_data *prog_data = &brw->tcs.prog_data->base.base;
+
+      _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_CTRL);
       gen6_upload_push_constants(brw, &tcp->program.Base, prog_data,
                                       stage_state, AUB_TRACE_VS_CONSTANTS);
    }
@@ -49,6 +52,7 @@ const struct brw_tracked_state gen7_tcs_push_constants = {
    .dirty = {
       .mesa  = _NEW_PROGRAM_CONSTANTS,
       .brw   = BRW_NEW_BATCH |
+               BRW_NEW_BLORP |
                BRW_NEW_DEFAULT_TESS_LEVELS |
                BRW_NEW_PUSH_CONSTANT_ALLOCATION |
                BRW_NEW_TESS_PROGRAMS |
@@ -82,7 +86,7 @@ gen7_upload_hs_state(struct brw_context *brw)
       if (prog_data->base.total_scratch) {
          OUT_RELOC(stage_state->scratch_bo,
                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                   ffs(prog_data->base.total_scratch) - 11);
+                   ffs(stage_state->per_thread_scratch) - 11);
       } else {
          OUT_BATCH(0);
       }
@@ -110,6 +114,7 @@ const struct brw_tracked_state gen7_hs_state = {
    .dirty = {
       .mesa  = 0,
       .brw   = BRW_NEW_BATCH |
+               BRW_NEW_BLORP |
                BRW_NEW_TCS_PROG_DATA |
                BRW_NEW_TESS_PROGRAMS,
    },