bool needs_dc = false, needs_slm = false;
for (unsigned i = 0; i < ARRAY_SIZE(stage_states); i++) {
- const struct gl_shader_program *prog =
+ const struct gl_program *prog =
brw->ctx._Shader->CurrentProgram[stage_states[i]->stage];
const struct brw_stage_prog_data *prog_data = stage_states[i]->prog_data;
- needs_dc |= (prog && prog->NumAtomicBuffers) ||
- (prog_data && (prog_data->total_scratch || prog_data->nr_image_params));
+ needs_dc |= (prog && (prog->sh.data->NumAtomicBuffers ||
+ prog->sh.data->NumShaderStorageBlocks ||
+ prog->info.num_images)) ||
+ (prog_data && prog_data->total_scratch);
needs_slm |= prog_data && prog_data->total_shared;
}
- return gen_get_default_l3_weights(brw->intelScreen->devinfo,
+ return gen_get_default_l3_weights(&brw->screen->devinfo,
needs_dc, needs_slm);
}
static void
setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
cfg->n[GEN_L3P_ALL];
*/
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DATA_CACHE_FLUSH |
- PIPE_CONTROL_NO_WRITE |
PIPE_CONTROL_CS_STALL);
/* ...followed by a second pipelined PIPE_CONTROL that initiates
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_INSTRUCTION_INVALIDATE |
- PIPE_CONTROL_STATE_CACHE_INVALIDATE |
- PIPE_CONTROL_NO_WRITE);
+ PIPE_CONTROL_STATE_CACHE_INVALIDATE);
/* Now send a third stalling flush to make sure that invalidation is
* complete when the L3 configuration registers are modified.
*/
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DATA_CACHE_FLUSH |
- PIPE_CONTROL_NO_WRITE |
PIPE_CONTROL_CS_STALL);
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
+ const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
+ (devinfo->gen == 11 ? GEN11_L3CNTLREG_USE_FULL_WAYS : 0) |
+ SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
+ SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
+ SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
+ SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
/* Set up the L3 partitioning. */
- OUT_BATCH(GEN8_L3CNTLREG);
- OUT_BATCH((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
- SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
- SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
- SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
- SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
-
- ADVANCE_BATCH();
-
+ brw_load_register_imm32(brw, GEN8_L3CNTLREG, imm_data);
} else {
assert(!cfg->n[GEN_L3P_ALL]);
* client (URB for all validated configurations) set to the
* lower-bandwidth 2-bank address hashing mode.
*/
- const bool urb_low_bw = has_slm && !brw->is_baytrail;
+ const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
/* Minimum number of ways that can be allocated to the URB. */
- const unsigned n0_urb = (brw->is_baytrail ? 32 : 0);
+ const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0);
assert(cfg->n[GEN_L3P_URB] >= n0_urb);
BEGIN_BATCH(7);
/* Demote any clients with no ways assigned to LLC. */
OUT_BATCH(GEN7_L3SQCREG1);
- OUT_BATCH((brw->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
- brw->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
+ OUT_BATCH((devinfo->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
+ devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
IVB_L3SQCREG1_SQGHPCI_DEFAULT) |
(has_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC) |
(has_is ? 0 : GEN7_L3SQCREG1_CONV_IS_UC) |
ADVANCE_BATCH();
- if (brw->is_haswell && brw->intelScreen->cmd_parser_version >= 4) {
+ if (can_do_hsw_l3_atomics(brw->screen)) {
/* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
* them disabled to avoid crashing the system hard.
*/
static void
update_urb_size(struct brw_context *brw, const struct gen_l3_config *cfg)
{
- const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
const unsigned sz = gen_get_l3_config_urb_size(devinfo, cfg);
if (brw->urb.size != sz) {
brw->urb.size = sz;
brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
+
+ /* If we change the total URB size, reset the individual stage sizes to
+ * zero so that, even if there is no URB size change, gen7_upload_urb
+ * still re-emits 3DSTATE_URB_*.
+ */
+ brw->urb.vsize = 0;
+ brw->urb.gsize = 0;
+ brw->urb.hsize = 0;
+ brw->urb.dsize = 0;
}
}
const float dw_threshold = (brw->ctx.NewDriverState & BRW_NEW_BATCH ?
small_dw_threshold : large_dw_threshold);
- if (dw > dw_threshold && brw->can_do_pipelined_register_writes) {
+ if (dw > dw_threshold && can_do_pipelined_register_writes(brw->screen)) {
const struct gen_l3_config *const cfg =
- gen_get_l3_config(brw->intelScreen->devinfo, w);
+ gen_get_l3_config(&brw->screen->devinfo, w);
setup_l3_config(brw, cfg);
update_urb_size(brw, cfg);
BRW_NEW_CS_PROG_DATA |
BRW_NEW_FS_PROG_DATA |
BRW_NEW_GS_PROG_DATA |
+ BRW_NEW_TCS_PROG_DATA |
+ BRW_NEW_TES_PROG_DATA |
BRW_NEW_VS_PROG_DATA,
},
.emit = emit_l3_state
void
gen7_restore_default_l3_config(struct brw_context *brw)
{
- const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
const struct gen_l3_config *const cfg = gen_get_default_l3_config(devinfo);
- if (cfg != brw->l3.config && brw->can_do_pipelined_register_writes) {
+ if (cfg != brw->l3.config &&
+ can_do_pipelined_register_writes(brw->screen)) {
setup_l3_config(brw, cfg);
update_urb_size(brw, cfg);
brw->l3.config = cfg;