const struct brw_stage_prog_data *prog_data = stage_states[i]->prog_data;
needs_dc |= (prog && (prog->sh.data->NumAtomicBuffers ||
- prog->sh.data->NumShaderStorageBlocks)) ||
- (prog_data && (prog_data->total_scratch || prog_data->nr_image_params));
+ prog->sh.data->NumShaderStorageBlocks ||
+ prog->info.num_images)) ||
+ (prog_data && prog_data->total_scratch);
needs_slm |= prog_data && prog_data->total_shared;
}
if (devinfo->gen >= 8) {
assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
+ const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
+ SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
+ SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
+ SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
+ SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
/* Set up the L3 partitioning. */
- OUT_BATCH(GEN8_L3CNTLREG);
- OUT_BATCH((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
- SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
- SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
- SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
- SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
-
- ADVANCE_BATCH();
-
+ brw_load_register_imm32(brw, GEN8_L3CNTLREG, imm_data);
} else {
assert(!cfg->n[GEN_L3P_ALL]);
BRW_NEW_CS_PROG_DATA |
BRW_NEW_FS_PROG_DATA |
BRW_NEW_GS_PROG_DATA |
+ BRW_NEW_TCS_PROG_DATA |
+ BRW_NEW_TES_PROG_DATA |
BRW_NEW_VS_PROG_DATA,
},
.emit = emit_l3_state