i965: perf: cleanup detection of kernel support for loadable configs

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_l3_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index a368af3631647d3ec02691b318a2f0687b31bd06..8c8f4169e7ea15819abfd712110f201f63d2a634 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -54,8 +54,9 @@ get_pipeline_state_l3_weights(const struct brw_context *brw)
       const struct brw_stage_prog_data *prog_data = stage_states[i]->prog_data;
 
       needs_dc |= (prog && (prog->sh.data->NumAtomicBuffers ||
-                            prog->sh.data->NumShaderStorageBlocks)) ||
-         (prog_data && (prog_data->total_scratch || prog_data->nr_image_params));
+                            prog->sh.data->NumShaderStorageBlocks ||
+                            prog->info.num_images)) ||
+         (prog_data && prog_data->total_scratch);
       needs_slm |= prog_data && prog_data->total_shared;
    }
 
@@ -120,19 +121,14 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
    if (devinfo->gen >= 8) {
       assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
 
-      BEGIN_BATCH(3);
-      OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
+      const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
+         SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
+         SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
+         SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
+         SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
 
       /* Set up the L3 partitioning. */
-      OUT_BATCH(GEN8_L3CNTLREG);
-      OUT_BATCH((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
-                SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
-                SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
-                SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
-                SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
-
-      ADVANCE_BATCH();
-
+      brw_load_register_imm32(brw, GEN8_L3CNTLREG, imm_data);
    } else {
       assert(!cfg->n[GEN_L3P_ALL]);
 
@@ -262,6 +258,8 @@ const struct brw_tracked_state gen7_l3_state = {
              BRW_NEW_CS_PROG_DATA |
              BRW_NEW_FS_PROG_DATA |
              BRW_NEW_GS_PROG_DATA |
+             BRW_NEW_TCS_PROG_DATA |
+             BRW_NEW_TES_PROG_DATA |
              BRW_NEW_VS_PROG_DATA,
    },
    .emit = emit_l3_state