mesa: Only expose GLES's EXT_texture_type_2_10_10_10_REV if supported in HW.

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_l3_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index 536c00c4543368196327f26b14c4e10e44d012d2..a368af3631647d3ec02691b318a2f0687b31bd06 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -69,6 +69,7 @@ get_pipeline_state_l3_weights(const struct brw_context *brw)
 static void
 setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
 {
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
    const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
                        cfg->n[GEN_L3P_ALL];
@@ -116,7 +117,7 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
                                PIPE_CONTROL_NO_WRITE |
                                PIPE_CONTROL_CS_STALL);
 
-   if (brw->gen >= 8) {
+   if (devinfo->gen >= 8) {
       assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
 
       BEGIN_BATCH(3);
@@ -140,11 +141,11 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
        * client (URB for all validated configurations) set to the
        * lower-bandwidth 2-bank address hashing mode.
        */
-      const bool urb_low_bw = has_slm && !brw->is_baytrail;
+      const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
       assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
 
       /* Minimum number of ways that can be allocated to the URB. */
-      const unsigned n0_urb = (brw->is_baytrail ? 32 : 0);
+      const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0);
       assert(cfg->n[GEN_L3P_URB] >= n0_urb);
 
       BEGIN_BATCH(7);
@@ -152,8 +153,8 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
 
       /* Demote any clients with no ways assigned to LLC. */
       OUT_BATCH(GEN7_L3SQCREG1);
-      OUT_BATCH((brw->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
-                 brw->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
+      OUT_BATCH((devinfo->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
+                 devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
                  IVB_L3SQCREG1_SQGHPCI_DEFAULT) |
                 (has_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC) |
                 (has_is ? 0 : GEN7_L3SQCREG1_CONV_IS_UC) |
@@ -204,6 +205,15 @@ update_urb_size(struct brw_context *brw, const struct gen_l3_config *cfg)
    if (brw->urb.size != sz) {
       brw->urb.size = sz;
       brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
+
+      /* If we change the total URB size, reset the individual stage sizes to
+       * zero so that, even if there is no URB size change, gen7_upload_urb
+       * still re-emits 3DSTATE_URB_*.
+       */
+      brw->urb.vsize = 0;
+      brw->urb.gsize = 0;
+      brw->urb.hsize = 0;
+      brw->urb.dsize = 0;
    }
 }