#include "main/mtypes.h"
#include "intel_batchbuffer.h"
#include "intel_mipmap_tree.h"
-#include "intel_regions.h"
#include "intel_fbo.h"
#include "brw_context.h"
#include "brw_state.h"
uint32_t tile_x, uint32_t tile_y)
{
struct gl_context *ctx = &brw->ctx;
- uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+ const uint8_t mocs = GEN7_MOCS_L3;
struct gl_framebuffer *fb = ctx->DrawBuffer;
uint32_t surftype;
+ unsigned int depth = 1;
+ unsigned int min_array_element;
GLenum gl_target = GL_TEXTURE_2D;
+ unsigned int lod;
+ const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
const struct intel_renderbuffer *irb = NULL;
const struct gl_renderbuffer *rb = NULL;
- intel_emit_depth_stall_flushes(brw);
+ /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
+ if (!mt && brw->no_depth_or_stencil) {
+ assert(brw->hw_ctx);
+ return;
+ }
+
+ brw_emit_depth_stall_flushes(brw);
irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
if (!irb)
rb = (struct gl_renderbuffer*) irb;
if (rb) {
+ depth = MAX2(irb->layer_count, 1);
if (rb->TexImage)
gl_target = rb->TexImage->TexObject->Target;
}
* equivalent.
*/
surftype = BRW_SURFACE_2D;
+ depth *= 6;
break;
+ case GL_TEXTURE_3D:
+ assert(mt);
+ depth = mt->surf.logical_level0_px.depth;
+ /* fallthrough */
default:
surftype = translate_tex_target(gl_target);
break;
}
+ min_array_element = irb ? irb->mt_layer : 0;
+
+ lod = irb ? irb->mt_level - irb->mt->first_level : 0;
+
+ if (mt) {
+ width = mt->surf.logical_level0_px.width;
+ height = mt->surf.logical_level0_px.height;
+ }
+
/* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
BEGIN_BATCH(7);
+ /* 3DSTATE_DEPTH_BUFFER dw0 */
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
- OUT_BATCH((depth_mt ? depth_mt->region->pitch - 1 : 0) |
+
+ /* 3DSTATE_DEPTH_BUFFER dw1 */
+ OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
(depthbuffer_format << 18) |
((hiz ? 1 : 0) << 22) |
- ((stencil_mt != NULL && ctx->Stencil._WriteEnabled) << 27) |
- ((ctx->Depth.Mask != 0) << 28) |
- (depth_surface_type << 29));
+ ((stencil_mt != NULL && brw->stencil_write_enabled) << 27) |
+ (brw_depth_writes_enabled(brw) << 28) |
+ (surftype << 29));
+ /* 3DSTATE_DEPTH_BUFFER dw2 */
if (depth_mt) {
- OUT_RELOC(depth_mt->region->bo,
+ OUT_RELOC(depth_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- depth_offset);
+ 0);
} else {
OUT_BATCH(0);
}
- OUT_BATCH(((width + tile_x - 1) << 4) |
- ((height + tile_y - 1) << 18));
- OUT_BATCH(mocs);
- OUT_BATCH(tile_x | (tile_y << 16));
+ /* 3DSTATE_DEPTH_BUFFER dw3 */
+ OUT_BATCH(((width - 1) << 4) |
+ ((height - 1) << 18) |
+ lod);
+
+ /* 3DSTATE_DEPTH_BUFFER dw4 */
+ OUT_BATCH(((depth - 1) << 21) |
+ (min_array_element << 10) |
+ mocs);
+
+ /* 3DSTATE_DEPTH_BUFFER dw5 */
OUT_BATCH(0);
+
+ /* 3DSTATE_DEPTH_BUFFER dw6 */
+ OUT_BATCH((depth - 1) << 21);
ADVANCE_BATCH();
if (!hiz) {
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
- struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
+ assert(depth_mt);
+
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH((mocs << 25) |
- (hiz_mt->region->pitch - 1));
- OUT_RELOC(hiz_mt->region->bo,
+ (depth_mt->hiz_buf->pitch - 1));
+ OUT_RELOC(depth_mt->hiz_buf->bo,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER,
- brw->depthstencil.hiz_offset);
+ 0);
ADVANCE_BATCH();
}
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
+ stencil_mt->r8stencil_needs_update = true;
const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0;
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
- /* The stencil buffer has quirky pitch requirements. From the
- * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
- * dword 1 bits 16:0 - Surface Pitch):
- *
- * The pitch must be set to 2x the value computed based on width, as
- * the stencil buffer is stored with two rows interleaved.
- *
- * While the Ivybridge PRM lacks this comment, the BSpec contains the
- * same text, and experiments indicate that this is necessary.
- */
OUT_BATCH(enabled |
mocs << 25 |
- (2 * stencil_mt->region->pitch - 1));
- OUT_RELOC(stencil_mt->region->bo,
+ (stencil_mt->surf.row_pitch - 1));
+ OUT_RELOC(stencil_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- brw->depthstencil.stencil_offset);
+ 0);
ADVANCE_BATCH();
}
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
- OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
+ if (depth_mt) {
+ OUT_BATCH(brw_convert_depth_value(depth_mt->format,
+ depth_mt->fast_clear_color.f32[0]));
+ } else {
+ OUT_BATCH(0);
+ }
OUT_BATCH(1);
ADVANCE_BATCH();
+
+ brw->no_depth_or_stencil = !mt;
}
/**
*/
const struct brw_tracked_state gen7_depthbuffer = {
.dirty = {
- .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
- .brw = BRW_NEW_BATCH,
- .cache = 0,
+ .mesa = _NEW_BUFFERS |
+ _NEW_DEPTH |
+ _NEW_STENCIL,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_BLORP,
},
.emit = brw_emit_depthbuffer,
};
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