i965: Add and use a single miptree aux_buf field

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_misc_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 16b08ed8687ddc6af85239a31c67f0cff6ac9aaf..1ce76585f2bd4d6173cd0a002ba5e0731e42059b 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -39,6 +39,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
                             uint32_t width, uint32_t height,
                             uint32_t tile_x, uint32_t tile_y)
 {
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct gl_context *ctx = &brw->ctx;
    const uint8_t mocs = GEN7_MOCS_L3;
    struct gl_framebuffer *fb = ctx->DrawBuffer;
@@ -83,7 +84,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       break;
    case GL_TEXTURE_3D:
       assert(mt);
-      depth = MAX2(mt->logical_depth0, 1);
+      depth = mt->surf.logical_level0_px.depth;
       /* fallthrough */
    default:
       surftype = translate_tex_target(gl_target);
@@ -95,8 +96,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 
    if (mt) {
-      width = mt->logical_width0;
-      height = mt->logical_height0;
+      width = mt->surf.logical_level0_px.width;
+      height = mt->surf.logical_level0_px.height;
    }
 
    /* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
@@ -105,18 +106,16 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 
    /* 3DSTATE_DEPTH_BUFFER dw1 */
-   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
+   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
              (depthbuffer_format << 18) |
              ((hiz ? 1 : 0) << 22) |
-             ((stencil_mt != NULL && ctx->Stencil._WriteEnabled) << 27) |
+             ((stencil_mt != NULL && brw->stencil_write_enabled) << 27) |
              (brw_depth_writes_enabled(brw) << 28) |
              (surftype << 29));
 
    /* 3DSTATE_DEPTH_BUFFER dw2 */
    if (depth_mt) {
-      OUT_RELOC(depth_mt->bo,
-               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-               0);
+      OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0);
    } else {
       OUT_BATCH(0);
    }
@@ -146,16 +145,12 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       ADVANCE_BATCH();
    } else {
       assert(depth_mt);
-      struct intel_miptree_hiz_buffer *hiz_buf = depth_mt->hiz_buf;
 
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
       OUT_BATCH((mocs << 25) |
-                (hiz_buf->aux_base.pitch - 1));
-      OUT_RELOC(hiz_buf->aux_base.bo,
-                I915_GEM_DOMAIN_RENDER,
-                I915_GEM_DOMAIN_RENDER,
-                0);
+                (depth_mt->aux_buf->pitch - 1));
+      OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, 0);
       ADVANCE_BATCH();
    }
 
@@ -167,26 +162,14 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       ADVANCE_BATCH();
    } else {
       stencil_mt->r8stencil_needs_update = true;
-      const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0;
+      const int enabled = devinfo->is_haswell ? HSW_STENCIL_ENABLED : 0;
 
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
-      /* The stencil buffer has quirky pitch requirements.  From the
-       * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
-       * dword 1 bits 16:0 - Surface Pitch):
-       *
-       *    The pitch must be set to 2x the value computed based on width, as
-       *    the stencil buffer is stored with two rows interleaved.
-       *
-       * While the Ivybridge PRM lacks this comment, the BSpec contains the
-       * same text, and experiments indicate that this is necessary.
-       */
       OUT_BATCH(enabled |
                 mocs << 25 |
-               (2 * stencil_mt->pitch - 1));
-      OUT_RELOC(stencil_mt->bo,
-               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-               0);
+               (stencil_mt->surf.row_pitch - 1));
+      OUT_RELOC(stencil_mt->bo, RELOC_WRITE, 0);
       ADVANCE_BATCH();
    }