i965: Add and use a single miptree aux_buf field

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_misc_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 8fb0eec7765140166b167f6111511d7f0fc6a4fe..1ce76585f2bd4d6173cd0a002ba5e0731e42059b 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -24,7 +24,6 @@
 #include "main/mtypes.h"
 #include "intel_batchbuffer.h"
 #include "intel_mipmap_tree.h"
-#include "intel_regions.h"
 #include "intel_fbo.h"
 #include "brw_context.h"
 #include "brw_state.h"
@@ -40,6 +39,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
                             uint32_t width, uint32_t height,
                             uint32_t tile_x, uint32_t tile_y)
 {
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct gl_context *ctx = &brw->ctx;
    const uint8_t mocs = GEN7_MOCS_L3;
    struct gl_framebuffer *fb = ctx->DrawBuffer;
@@ -52,7 +52,13 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
    const struct intel_renderbuffer *irb = NULL;
    const struct gl_renderbuffer *rb = NULL;
 
-   intel_emit_depth_stall_flushes(brw);
+   /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
+   if (!mt && brw->no_depth_or_stencil) {
+      assert(brw->hw_ctx);
+      return;
+   }
+
+   brw_emit_depth_stall_flushes(brw);
 
    irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
    if (!irb)
@@ -60,7 +66,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
    rb = (struct gl_renderbuffer*) irb;
 
    if (rb) {
-      depth = MAX2(rb->Depth, 1);
+      depth = MAX2(irb->layer_count, 1);
       if (rb->TexImage)
          gl_target = rb->TexImage->TexObject->Target;
    }
@@ -76,25 +82,22 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       surftype = BRW_SURFACE_2D;
       depth *= 6;
       break;
+   case GL_TEXTURE_3D:
+      assert(mt);
+      depth = mt->surf.logical_level0_px.depth;
+      /* fallthrough */
    default:
       surftype = translate_tex_target(gl_target);
       break;
    }
 
-   if (fb->MaxNumLayers > 0 || !irb) {
-      min_array_element = 0;
-   } else if (irb->mt->num_samples > 1) {
-      /* Convert physical layer to logical layer. */
-      min_array_element = irb->mt_layer / irb->mt->num_samples;
-   } else {
-      min_array_element = irb->mt_layer;
-   }
+   min_array_element = irb ? irb->mt_layer : 0;
 
    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 
    if (mt) {
-      width = mt->logical_width0;
-      height = mt->logical_height0;
+      width = mt->surf.logical_level0_px.width;
+      height = mt->surf.logical_level0_px.height;
    }
 
    /* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
@@ -103,18 +106,16 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 
    /* 3DSTATE_DEPTH_BUFFER dw1 */
-   OUT_BATCH((depth_mt ? depth_mt->region->pitch - 1 : 0) |
+   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
              (depthbuffer_format << 18) |
              ((hiz ? 1 : 0) << 22) |
-             ((stencil_mt != NULL && ctx->Stencil._WriteEnabled) << 27) |
-             ((ctx->Depth.Mask != 0) << 28) |
+             ((stencil_mt != NULL && brw->stencil_write_enabled) << 27) |
+             (brw_depth_writes_enabled(brw) << 28) |
              (surftype << 29));
 
    /* 3DSTATE_DEPTH_BUFFER dw2 */
    if (depth_mt) {
-      OUT_RELOC(depth_mt->region->bo,
-               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-               0);
+      OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0);
    } else {
       OUT_BATCH(0);
    }
@@ -143,15 +144,13 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       OUT_BATCH(0);
       ADVANCE_BATCH();
    } else {
-      struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
+      assert(depth_mt);
+
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
       OUT_BATCH((mocs << 25) |
-                (hiz_mt->region->pitch - 1));
-      OUT_RELOC(hiz_mt->region->bo,
-                I915_GEM_DOMAIN_RENDER,
-                I915_GEM_DOMAIN_RENDER,
-                0);
+                (depth_mt->aux_buf->pitch - 1));
+      OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, 0);
       ADVANCE_BATCH();
    }
 
@@ -162,34 +161,30 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       OUT_BATCH(0);
       ADVANCE_BATCH();
    } else {
-      const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0;
+      stencil_mt->r8stencil_needs_update = true;
+      const int enabled = devinfo->is_haswell ? HSW_STENCIL_ENABLED : 0;
 
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
-      /* The stencil buffer has quirky pitch requirements.  From the
-       * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
-       * dword 1 bits 16:0 - Surface Pitch):
-       *
-       *    The pitch must be set to 2x the value computed based on width, as
-       *    the stencil buffer is stored with two rows interleaved.
-       *
-       * While the Ivybridge PRM lacks this comment, the BSpec contains the
-       * same text, and experiments indicate that this is necessary.
-       */
       OUT_BATCH(enabled |
                 mocs << 25 |
-               (2 * stencil_mt->region->pitch - 1));
-      OUT_RELOC(stencil_mt->region->bo,
-               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-               0);
+               (stencil_mt->surf.row_pitch - 1));
+      OUT_RELOC(stencil_mt->bo, RELOC_WRITE, 0);
       ADVANCE_BATCH();
    }
 
    BEGIN_BATCH(3);
    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
-   OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
+   if (depth_mt) {
+      OUT_BATCH(brw_convert_depth_value(depth_mt->format,
+                                        depth_mt->fast_clear_color.f32[0]));
+   } else {
+      OUT_BATCH(0);
+   }
    OUT_BATCH(1);
    ADVANCE_BATCH();
+
+   brw->no_depth_or_stencil = !mt;
 }
 
 /**
@@ -197,9 +192,11 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
  */
 const struct brw_tracked_state gen7_depthbuffer = {
    .dirty = {
-      .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
-      .brw = BRW_NEW_BATCH,
-      .cache = 0,
+      .mesa = _NEW_BUFFERS |
+              _NEW_DEPTH |
+              _NEW_STENCIL,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_BLORP,
    },
    .emit = brw_emit_depthbuffer,
 };