i965/nir/vec4: Implement single-element "mov" operations

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_misc_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 22911bf5423db5232a9e06999d8a97585d60cd78..a14d4a0c50dfddb647c29ba5776a62a45fd71ac0 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -57,7 +57,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       return;
    }
 
-   intel_emit_depth_stall_flushes(brw);
+   brw_emit_depth_stall_flushes(brw);
 
    irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
    if (!irb)
@@ -145,12 +145,13 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       OUT_BATCH(0);
       ADVANCE_BATCH();
    } else {
-      struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
+      struct intel_miptree_aux_buffer *hiz_buf = depth_mt->hiz_buf;
+
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
       OUT_BATCH((mocs << 25) |
-                (hiz_mt->pitch - 1));
-      OUT_RELOC(hiz_mt->bo,
+                (hiz_buf->pitch - 1));
+      OUT_RELOC(hiz_buf->bo,
                 I915_GEM_DOMAIN_RENDER,
                 I915_GEM_DOMAIN_RENDER,
                 0);
@@ -201,9 +202,10 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
  */
 const struct brw_tracked_state gen7_depthbuffer = {
    .dirty = {
-      .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
+      .mesa = _NEW_BUFFERS |
+              _NEW_DEPTH |
+              _NEW_STENCIL,
       .brw = BRW_NEW_BATCH,
-      .cache = 0,
    },
    .emit = brw_emit_depthbuffer,
 };