i965/gen7: Enable HiZ

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_misc_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 3946cb3d1d55e0632f00b1da579c24d4ec0d2cfb..f28748597a11335a20e4f86059c8fc3b7b843c01 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -38,11 +38,16 @@ static void emit_depthbuffer(struct brw_context *brw)
    /* _NEW_BUFFERS */
    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
    struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
-   struct intel_mipmap_tree *depth_mt = NULL, *stencil_mt = NULL;
+   struct intel_mipmap_tree *depth_mt = NULL,
+                           *stencil_mt = NULL,
+                           *hiz_mt = NULL;
 
    if (drb)
       depth_mt = drb->mt;
 
+   if (depth_mt)
+      hiz_mt = depth_mt->hiz_mt;
+
    if (srb) {
       stencil_mt = srb->mt;
       if (stencil_mt->stencil_mt)
@@ -53,6 +58,7 @@ static void emit_depthbuffer(struct brw_context *brw)
 
    /* Gen7 doesn't support packed depth/stencil */
    assert(stencil_mt == NULL || depth_mt != stencil_mt);
+   assert(!depth_mt || !_mesa_is_format_packed_depth_stencil(depth_mt->format));
 
    intel_emit_depth_stall_flushes(intel);
 
@@ -70,7 +76,8 @@ static void emit_depthbuffer(struct brw_context *brw)
 
         /* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */
         dw1 |= (BRW_SURFACE_2D << 29);
-        dw3 = ((region->width - 1) << 4) | ((2 * region->height - 1) << 18);
+        dw3 = ((srb->Base.Width - 1) << 4) |
+              ((srb->Base.Height - 1) << 18);
       }
 
       BEGIN_BATCH(7);
@@ -95,26 +102,37 @@ static void emit_depthbuffer(struct brw_context *brw)
       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
       OUT_BATCH(((region->pitch * region->cpp) - 1) |
                (brw_depthbuffer_format(brw) << 18) |
-               (0 << 22) /* no HiZ buffer */ |
+               ((hiz_mt ? 1 : 0) << 22) | /* hiz enable */
                ((stencil_mt != NULL && ctx->Stencil.WriteMask != 0) << 27) |
                ((ctx->Depth.Mask != 0) << 28) |
                (BRW_SURFACE_2D << 29));
       OUT_RELOC(region->bo,
                I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                offset);
-      OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18));
+      OUT_BATCH(((drb->Base.Width - 1) << 4) |
+                ((drb->Base.Height - 1) << 18));
       OUT_BATCH(0);
       OUT_BATCH(tile_x | (tile_y << 16));
       OUT_BATCH(0);
       ADVANCE_BATCH();
    }
 
-   BEGIN_BATCH(4);
-   OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (4 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
+   if (hiz_mt == NULL) {
+      BEGIN_BATCH(5);
+      OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+   } else {
+      BEGIN_BATCH(5);
+      OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
+      OUT_BATCH(hiz_mt->region->pitch * hiz_mt->region->cpp - 1);
+      OUT_RELOC(hiz_mt->region->bo,
+                I915_GEM_DOMAIN_RENDER,
+                I915_GEM_DOMAIN_RENDER,
+                0);
+      ADVANCE_BATCH();
+   }
 
    if (stencil_mt == NULL) {
       BEGIN_BATCH(3);