i965/gen7: Enable HiZ

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_misc_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 6a3c086ac96b9865b5ee558d25efeb391335e930..f28748597a11335a20e4f86059c8fc3b7b843c01 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -22,40 +22,13 @@
  */
 
 #include "intel_batchbuffer.h"
+#include "intel_mipmap_tree.h"
 #include "intel_regions.h"
 #include "intel_fbo.h"
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
 
-unsigned int
-gen7_depth_format(struct brw_context *brw)
-{
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
-   struct gl_framebuffer *fb = ctx->DrawBuffer;
-   struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
-   struct intel_region *region = NULL;
-
-   if (drb)
-      region = drb->region;
-   else
-      return BRW_DEPTHFORMAT_D32_FLOAT;
-
-   switch (region->cpp) {
-   case 2:
-      return BRW_DEPTHFORMAT_D16_UNORM;
-   case 4:
-      if (intel->depth_buffer_is_float)
-        return BRW_DEPTHFORMAT_D32_FLOAT;
-      else
-        return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
-   default:
-      assert(!"Should not get here.");
-   }
-   return 0;
-}
-
 static void emit_depthbuffer(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
@@ -65,27 +38,46 @@ static void emit_depthbuffer(struct brw_context *brw)
    /* _NEW_BUFFERS */
    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
    struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+   struct intel_mipmap_tree *depth_mt = NULL,
+                           *stencil_mt = NULL,
+                           *hiz_mt = NULL;
 
-   intel_emit_depth_stall_flushes(intel);
+   if (drb)
+      depth_mt = drb->mt;
+
+   if (depth_mt)
+      hiz_mt = depth_mt->hiz_mt;
+
+   if (srb) {
+      stencil_mt = srb->mt;
+      if (stencil_mt->stencil_mt)
+        stencil_mt = stencil_mt->stencil_mt;
+
+      assert(stencil_mt->format == MESA_FORMAT_S8);
+   }
 
    /* Gen7 doesn't support packed depth/stencil */
-   assert(srb == NULL || srb != drb);
+   assert(stencil_mt == NULL || depth_mt != stencil_mt);
+   assert(!depth_mt || !_mesa_is_format_packed_depth_stencil(depth_mt->format));
+
+   intel_emit_depth_stall_flushes(intel);
 
-   if (drb == NULL) {
+   if (depth_mt == NULL) {
       uint32_t dw1 = BRW_DEPTHFORMAT_D32_FLOAT << 18;
       uint32_t dw3 = 0;
 
-      if (srb == NULL) {
+      if (stencil_mt == NULL) {
         dw1 |= (BRW_SURFACE_NULL << 29);
       } else {
-        struct intel_region *region = srb->region;
+        struct intel_region *region = stencil_mt->region;
 
         /* _NEW_STENCIL: enable stencil buffer writes */
         dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);
 
         /* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */
         dw1 |= (BRW_SURFACE_2D << 29);
-        dw3 = ((region->width - 1) << 4) | ((2 * region->height - 1) << 18);
+        dw3 = ((srb->Base.Width - 1) << 4) |
+              ((srb->Base.Height - 1) << 18);
       }
 
       BEGIN_BATCH(7);
@@ -98,7 +90,7 @@ static void emit_depthbuffer(struct brw_context *brw)
       OUT_BATCH(0);
       ADVANCE_BATCH();
    } else {
-      struct intel_region *region = drb->region;
+      struct intel_region *region = depth_mt->region;
       uint32_t tile_x, tile_y, offset;
 
       offset = intel_renderbuffer_tile_offsets(drb, &tile_x, &tile_y);
@@ -109,29 +101,40 @@ static void emit_depthbuffer(struct brw_context *brw)
       BEGIN_BATCH(7);
       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
       OUT_BATCH(((region->pitch * region->cpp) - 1) |
-               (gen7_depth_format(brw) << 18) |
-               (0 << 22) /* no HiZ buffer */ |
-               ((srb != NULL && ctx->Stencil.WriteMask != 0) << 27) |
+               (brw_depthbuffer_format(brw) << 18) |
+               ((hiz_mt ? 1 : 0) << 22) | /* hiz enable */
+               ((stencil_mt != NULL && ctx->Stencil.WriteMask != 0) << 27) |
                ((ctx->Depth.Mask != 0) << 28) |
                (BRW_SURFACE_2D << 29));
       OUT_RELOC(region->bo,
                I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                offset);
-      OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18));
+      OUT_BATCH(((drb->Base.Width - 1) << 4) |
+                ((drb->Base.Height - 1) << 18));
       OUT_BATCH(0);
       OUT_BATCH(tile_x | (tile_y << 16));
       OUT_BATCH(0);
       ADVANCE_BATCH();
    }
 
-   BEGIN_BATCH(4);
-   OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (4 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
+   if (hiz_mt == NULL) {
+      BEGIN_BATCH(5);
+      OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+   } else {
+      BEGIN_BATCH(5);
+      OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
+      OUT_BATCH(hiz_mt->region->pitch * hiz_mt->region->cpp - 1);
+      OUT_RELOC(hiz_mt->region->bo,
+                I915_GEM_DOMAIN_RENDER,
+                I915_GEM_DOMAIN_RENDER,
+                0);
+      ADVANCE_BATCH();
+   }
 
-   if (srb == NULL) {
+   if (stencil_mt == NULL) {
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
       OUT_BATCH(0);
@@ -140,8 +143,8 @@ static void emit_depthbuffer(struct brw_context *brw)
    } else {
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
-      OUT_BATCH(srb->region->pitch * srb->region->cpp - 1);
-      OUT_RELOC(srb->region->bo,
+      OUT_BATCH(stencil_mt->region->pitch * stencil_mt->region->cpp - 1);
+      OUT_RELOC(stencil_mt->region->bo,
                I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                0);
       ADVANCE_BATCH();