* IN THE SOFTWARE.
*/
+#include "main/mtypes.h"
#include "intel_batchbuffer.h"
-#include "intel_regions.h"
+#include "intel_mipmap_tree.h"
#include "intel_fbo.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
-unsigned int
-gen7_depth_format(struct brw_context *brw)
+void
+gen7_emit_depth_stencil_hiz(struct brw_context *brw,
+ struct intel_mipmap_tree *depth_mt,
+ uint32_t depth_offset, uint32_t depthbuffer_format,
+ uint32_t depth_surface_type,
+ struct intel_mipmap_tree *stencil_mt,
+ bool hiz, bool separate_stencil,
+ uint32_t width, uint32_t height,
+ uint32_t tile_x, uint32_t tile_y)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
+ const uint8_t mocs = GEN7_MOCS_L3;
struct gl_framebuffer *fb = ctx->DrawBuffer;
- struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
- struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
- struct intel_region *region = NULL;
-
- if (drb)
- region = drb->region;
- else if (srb)
- region = srb->region;
- else
- return BRW_DEPTHFORMAT_D32_FLOAT;
-
- switch (region->cpp) {
- case 2:
- return BRW_DEPTHFORMAT_D16_UNORM;
- case 4:
- if (intel->depth_buffer_is_float)
- return BRW_DEPTHFORMAT_D32_FLOAT;
- else
- return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
+ uint32_t surftype;
+ unsigned int depth = 1;
+ unsigned int min_array_element;
+ GLenum gl_target = GL_TEXTURE_2D;
+ unsigned int lod;
+ const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
+ const struct intel_renderbuffer *irb = NULL;
+ const struct gl_renderbuffer *rb = NULL;
+
+ /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
+ if (!mt && brw->no_depth_or_stencil) {
+ assert(brw->hw_ctx);
+ return;
+ }
+
+ intel_emit_depth_stall_flushes(brw);
+
+ irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
+ if (!irb)
+ irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+ rb = (struct gl_renderbuffer*) irb;
+
+ if (rb) {
+ depth = MAX2(irb->layer_count, 1);
+ if (rb->TexImage)
+ gl_target = rb->TexImage->TexObject->Target;
+ }
+
+ switch (gl_target) {
+ case GL_TEXTURE_CUBE_MAP_ARRAY:
+ case GL_TEXTURE_CUBE_MAP:
+ /* The PRM claims that we should use BRW_SURFACE_CUBE for this
+ * situation, but experiments show that gl_Layer doesn't work when we do
+ * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
+ * equivalent.
+ */
+ surftype = BRW_SURFACE_2D;
+ depth *= 6;
+ break;
+ case GL_TEXTURE_3D:
+ assert(mt);
+ depth = MAX2(mt->logical_depth0, 1);
+ /* fallthrough */
default:
- assert(!"Should not get here.");
+ surftype = translate_tex_target(gl_target);
+ break;
}
- return 0;
-}
-static void emit_depthbuffer(struct brw_context *brw)
-{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
- struct gl_framebuffer *fb = ctx->DrawBuffer;
- struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
- struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
- struct intel_region *region = NULL;
-
- /* _NEW_BUFFERS */
- if (drb)
- region = drb->region;
- else if (srb)
- region = srb->region;
-
- if (region == NULL) {
- BEGIN_BATCH(7);
- OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
- OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
- (BRW_SURFACE_NULL << 29));
- OUT_BATCH(0);
- OUT_BATCH(0);
+ min_array_element = irb ? irb->mt_layer : 0;
+
+ lod = irb ? irb->mt_level - irb->mt->first_level : 0;
+
+ if (mt) {
+ width = mt->logical_width0;
+ height = mt->logical_height0;
+ }
+
+ /* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
+ BEGIN_BATCH(7);
+ /* 3DSTATE_DEPTH_BUFFER dw0 */
+ OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
+
+ /* 3DSTATE_DEPTH_BUFFER dw1 */
+ OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
+ (depthbuffer_format << 18) |
+ ((hiz ? 1 : 0) << 22) |
+ ((stencil_mt != NULL && ctx->Stencil._WriteEnabled) << 27) |
+ ((ctx->Depth.Mask != 0) << 28) |
+ (surftype << 29));
+
+ /* 3DSTATE_DEPTH_BUFFER dw2 */
+ if (depth_mt) {
+ OUT_RELOC(depth_mt->bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ 0);
+ } else {
OUT_BATCH(0);
+ }
+
+ /* 3DSTATE_DEPTH_BUFFER dw3 */
+ OUT_BATCH(((width - 1) << 4) |
+ ((height - 1) << 18) |
+ lod);
+
+ /* 3DSTATE_DEPTH_BUFFER dw4 */
+ OUT_BATCH(((depth - 1) << 21) |
+ (min_array_element << 10) |
+ mocs);
+
+ /* 3DSTATE_DEPTH_BUFFER dw5 */
+ OUT_BATCH(0);
+
+ /* 3DSTATE_DEPTH_BUFFER dw6 */
+ OUT_BATCH((depth - 1) << 21);
+ ADVANCE_BATCH();
+
+ if (!hiz) {
+ BEGIN_BATCH(3);
+ OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
- uint32_t tile_x, tile_y, offset;
+ struct intel_miptree_aux_buffer *hiz_buf = depth_mt->hiz_buf;
- offset = intel_region_tile_offsets(region, &tile_x, &tile_y);
-
- assert(region->tiling == I915_TILING_Y);
+ BEGIN_BATCH(3);
+ OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
+ OUT_BATCH((mocs << 25) |
+ (hiz_buf->pitch - 1));
+ OUT_RELOC(hiz_buf->bo,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER,
+ 0);
+ ADVANCE_BATCH();
+ }
- BEGIN_BATCH(7);
- OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
- OUT_BATCH(((region->pitch * region->cpp) - 1) |
- (gen7_depth_format(brw) << 18) |
- (0 << 22) /* no HiZ buffer */ |
- (0 << 27) /* no stencil write */ |
- ((ctx->Depth.Mask != 0) << 28) |
- (BRW_SURFACE_2D << 29));
- OUT_RELOC(region->buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- offset);
- OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18));
+ if (stencil_mt == NULL) {
+ BEGIN_BATCH(3);
+ OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
OUT_BATCH(0);
- OUT_BATCH(tile_x | (tile_y << 16));
OUT_BATCH(0);
ADVANCE_BATCH();
- }
-
- BEGIN_BATCH(4);
- OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (4 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
+ } else {
+ const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0;
- BEGIN_BATCH(4);
- OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (4 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
+ BEGIN_BATCH(3);
+ OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
+ /* The stencil buffer has quirky pitch requirements. From the
+ * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
+ * dword 1 bits 16:0 - Surface Pitch):
+ *
+ * The pitch must be set to 2x the value computed based on width, as
+ * the stencil buffer is stored with two rows interleaved.
+ *
+ * While the Ivybridge PRM lacks this comment, the BSpec contains the
+ * same text, and experiments indicate that this is necessary.
+ */
+ OUT_BATCH(enabled |
+ mocs << 25 |
+ (2 * stencil_mt->pitch - 1));
+ OUT_RELOC(stencil_mt->bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ 0);
+ ADVANCE_BATCH();
+ }
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
+ OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
+ OUT_BATCH(1);
ADVANCE_BATCH();
+
+ brw->no_depth_or_stencil = !mt;
}
/**
*/
const struct brw_tracked_state gen7_depthbuffer = {
.dirty = {
- .mesa = _NEW_BUFFERS,
+ .mesa = _NEW_BUFFERS |
+ _NEW_DEPTH |
+ _NEW_STENCIL,
.brw = BRW_NEW_BATCH,
- .cache = 0,
},
- .emit = emit_depthbuffer,
+ .emit = brw_emit_depthbuffer,
};
projects / mesa.git / blobdiff