i965: Refactor SIMD16-to-2xSIMD8 checks.

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_sf_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index ae6bf13d6cdeece1c7719de397eda65a2d9de829..c9815b03bb47f442ee05293aca7920246a3ad149 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -93,10 +93,10 @@ const struct brw_tracked_state gen7_sbe_state = {
                _NEW_PROGRAM,
       .brw   = BRW_NEW_CONTEXT |
                BRW_NEW_FRAGMENT_PROGRAM |
+               BRW_NEW_FS_PROG_DATA |
                BRW_NEW_GEOMETRY_PROGRAM |
                BRW_NEW_PRIMITIVE |
                BRW_NEW_VUE_MAP_GEOM_OUT,
-      .cache = BRW_NEW_FS_PROG_DATA
    },
    .emit = upload_sbe_state,
 };
@@ -192,8 +192,12 @@ upload_sf_state(struct brw_context *brw)
 
    /* _NEW_LINE */
    {
-      uint32_t line_width_u3_7 =
-         U_FIXED(CLAMP(ctx->Line.Width, 0.0, ctx->Const.MaxLineWidth), 7);
+      /* OpenGL dictates that line width should be rounded to the nearest
+       * integer
+       */
+      float line_width =
+         roundf(CLAMP(ctx->Line.Width, 0.0, ctx->Const.MaxLineWidth));
+      uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
       /* TODO: line width of 0 is not allowed when MSAA enabled */
       if (line_width_u3_7 == 0)
          line_width_u3_7 = 1;
@@ -242,7 +246,7 @@ upload_sf_state(struct brw_context *brw)
    OUT_BATCH(dw3);
    OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant.  copied from gen4 */
    OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
-   OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
+   OUT_BATCH_F(ctx->Polygon.OffsetClamp); /* global depth offset clamp */
    ADVANCE_BATCH();
 }
 
@@ -257,7 +261,6 @@ const struct brw_tracked_state gen7_sf_state = {
                _NEW_PROGRAM |
                _NEW_SCISSOR,
       .brw   = BRW_NEW_CONTEXT,
-      .cache = 0,
    },
    .emit = upload_sf_state,
 };