i965/nir/vec4: Implement single-element "mov" operations

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_sol_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index 3f99df9dd9112bb153225cc3f92c95a6c2e2e55f..41573a80a52dfe3ec6719e68fe16002afb2a37df 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -164,7 +164,7 @@ gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
        * for fake "hole" components, rather than simply taking the offset
        * for each real varying.  Each hole can have size 1, 2, 3, or 4; we
        * program as many size = 4 holes as we can, then a final hole to
-       * accomodate the final 1, 2, or 3 remaining.
+       * accommodate the final 1, 2, or 3 remaining.
        */
       int skip_components =
          linked_xfb_info->Outputs[i].DstOffset - next_offset[buffer];
@@ -365,7 +365,7 @@ gen7_save_primitives_written_counters(struct brw_context *brw,
    }
 
    /* Flush any drawing so that the counters have the right values. */
-   intel_batchbuffer_emit_mi_flush(brw);
+   brw_emit_mi_flush(brw);
 
    /* Emit MI_STORE_REGISTER_MEM commands to write the values. */
    for (int i = 0; i < streams; i++) {
@@ -502,7 +502,7 @@ gen7_pause_transform_feedback(struct gl_context *ctx,
       (struct brw_transform_feedback_object *) obj;
 
    /* Flush any drawing so that the counters have the right values. */
-   intel_batchbuffer_emit_mi_flush(brw);
+   brw_emit_mi_flush(brw);
 
    /* Save the SOL buffer offset register values. */
    if (brw->gen < 8) {