i965/fs: Add support for translating ir_triop_fma into MAD.

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_sol_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index 8dfac01ff022e40881a15ddfca84570dccb4cfe7..fc69bfc261eecdee3f8b91e44d415d14ec043ee9 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -38,8 +38,7 @@
 static void
 upload_3dstate_so_buffers(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
+   struct gl_context *ctx = &brw->ctx;
    /* BRW_NEW_VERTEX_PROGRAM */
    const struct gl_shader_program *vs_prog =
       ctx->Shader.CurrentVertexProgram;
@@ -74,7 +73,7 @@ upload_3dstate_so_buffers(struct brw_context *brw)
         continue;
       }
 
-      bo = intel_bufferobj_buffer(intel, bufferobj, INTEL_WRITE_PART);
+      bo = intel_bufferobj_buffer(brw, bufferobj, INTEL_WRITE_PART);
       stride = linked_xfb_info->BufferStride[i] * 4;
 
       start = xfb_obj->Offset[i];
@@ -98,12 +97,11 @@ upload_3dstate_so_buffers(struct brw_context *brw)
  * stream.  We only have one stream of rendering coming out of the GS unit, so
  * we only emit stream 0 (low 16 bits) SO_DECLs.
  */
-static void
-upload_3dstate_so_decl_list(struct brw_context *brw,
-                           const struct brw_vue_map *vue_map)
+void
+gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
+                                 const struct brw_vue_map *vue_map)
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
+   struct gl_context *ctx = &brw->ctx;
    /* BRW_NEW_VERTEX_PROGRAM */
    const struct gl_shader_program *vs_prog =
       ctx->Shader.CurrentVertexProgram;
@@ -178,8 +176,7 @@ static void
 upload_3dstate_streamout(struct brw_context *brw, bool active,
                         const struct brw_vue_map *vue_map)
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
+   struct gl_context *ctx = &brw->ctx;
    /* BRW_NEW_TRANSFORM_FEEDBACK */
    struct gl_transform_feedback_object *xfb_obj =
       ctx->TransformFeedback.CurrentObject;
@@ -223,15 +220,14 @@ upload_3dstate_streamout(struct brw_context *brw, bool active,
 static void
 upload_sol_state(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
+   struct gl_context *ctx = &brw->ctx;
    /* BRW_NEW_TRANSFORM_FEEDBACK */
    bool active = _mesa_is_xfb_active_and_unpaused(ctx);
 
    if (active) {
       upload_3dstate_so_buffers(brw);
       /* BRW_NEW_VUE_MAP_GEOM_OUT */
-      upload_3dstate_so_decl_list(brw, &brw->vue_map_geom_out);
+      gen7_upload_3dstate_so_decl_list(brw, &brw->vue_map_geom_out);
    }
 
    /* Finally, set up the SOL stage.  This command must always follow updates to
@@ -258,16 +254,9 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
                               struct gl_transform_feedback_object *obj)
 {
    struct brw_context *brw = brw_context(ctx);
-   struct intel_context *intel = &brw->intel;
 
-   /* Reset the SOL buffer offset register. */
-   for (int i = 0; i < 4; i++) {
-      BEGIN_BATCH(3);
-      OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
-      OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-   }
+   intel_batchbuffer_flush(brw);
+   brw->batch.needs_sol_reset = true;
 }
 
 void
@@ -281,7 +270,6 @@ gen7_end_transform_feedback(struct gl_context *ctx,
     * This also covers any cache flushing required.
     */
    struct brw_context *brw = brw_context(ctx);
-   struct intel_context *intel = &brw->intel;
 
-   intel_batchbuffer_flush(intel);
+   intel_batchbuffer_flush(brw);
 }