i965/fs: Return more accurate read size from fs_inst::size_read for IMM and UNIFORM...

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_te_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_te_state.c b/src/mesa/drivers/dri/i965/gen7_te_state.c
index 95a5e98133b86c2724f7984d520fbb6685f73bc9..d525318f71c6bf56a7a27f2fb0aa6ed5fb35d09f 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_te_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_te_state.c
@@ -29,19 +29,38 @@
 static void
 upload_te_state(struct brw_context *brw)
 {
-   /* Disable the TE */
-   BEGIN_BATCH(4);
-   OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
+   /* BRW_NEW_TESS_PROGRAMS */
+   bool active = brw->tess_eval_program;
+
+   const struct brw_tes_prog_data *tes_prog_data = brw->tes.prog_data;
+
+   if (active) {
+      BEGIN_BATCH(4);
+      OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
+      OUT_BATCH((tes_prog_data->partitioning << GEN7_TE_PARTITIONING_SHIFT) |
+                (tes_prog_data->output_topology << GEN7_TE_OUTPUT_TOPOLOGY_SHIFT) |
+                (tes_prog_data->domain << GEN7_TE_DOMAIN_SHIFT) |
+                GEN7_TE_ENABLE);
+      OUT_BATCH_F(63.0);
+      OUT_BATCH_F(64.0);
+      ADVANCE_BATCH();
+   } else {
+      BEGIN_BATCH(4);
+      OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH_F(0);
+      OUT_BATCH_F(0);
+      ADVANCE_BATCH();
+   }
 }
 
 const struct brw_tracked_state gen7_te_state = {
    .dirty = {
       .mesa  = 0,
-      .brw   = BRW_NEW_CONTEXT,
+      .brw   = BRW_NEW_BLORP |
+               BRW_NEW_CONTEXT |
+               BRW_NEW_TES_PROG_DATA |
+               BRW_NEW_TESS_PROGRAMS,
    },
    .emit = upload_te_state,
 };