i965/fs: Add support for translating ir_triop_fma into MAD.

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_urb.c

diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
index 2b650e9bc453b12da4327e1190982e73ee46df81..350f644dfcdcfa2dfc703c070703fc458fb83551 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -39,27 +39,48 @@
  * +-------------------------------------------------------------+
  *
  * Notably, push constants must be stored at the beginning of the URB
- * space, while entries can be stored anywhere.  Ivybridge has a maximum
- * constant buffer size of 16kB.
+ * space, while entries can be stored anywhere.  Ivybridge and Haswell
+ * GT1/GT2 have a maximum constant buffer size of 16kB, while Haswell GT3
+ * doubles this (32kB).
  *
  * Currently we split the constant buffer space evenly between VS and FS.
  * This is probably not ideal, but simple.
  *
- * Ivybridge GT1 has 128kB of URB space.
- * Ivybridge GT2 has 256kB of URB space.
+ * Ivybridge GT1 and Haswell GT1 have 128kB of URB space.
+ * Ivybridge GT2 and Haswell GT2 have 256kB of URB space.
+ * Haswell GT3 has 512kB of URB space.
  *
- * See "Volume 2a: 3D Pipeline," section 1.8.
+ * See "Volume 2a: 3D Pipeline," section 1.8, "Volume 1b: Configurations",
+ * and the documentation for 3DSTATE_PUSH_CONSTANT_ALLOC_xS.
  */
+void
+gen7_allocate_push_constants(struct brw_context *brw)
+{
+   unsigned size = 8;
+   if (brw->is_haswell && brw->gt == 3)
+      size = 16;
+
+   BEGIN_BATCH(4);
+   OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2));
+   OUT_BATCH(size);
+
+   OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2));
+   OUT_BATCH(size | size << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
+   ADVANCE_BATCH();
+}
+
 static void
-prepare_urb(struct brw_context *brw)
+gen7_upload_urb(struct brw_context *brw)
 {
+   const int push_size_kB = brw->is_haswell && brw->gt == 3 ? 32 : 16;
+
    /* Total space for entries is URB size - 16kB for push constants */
-   int handle_region_size = (brw->urb.size - 16) * 1024; /* bytes */
+   int handle_region_size = (brw->urb.size - push_size_kB) * 1024; /* bytes */
 
    /* CACHE_NEW_VS_PROG */
-   brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1);
+   unsigned vs_size = MAX2(brw->vs.prog_data->base.urb_entry_size, 1);
 
-   int nr_vs_entries = handle_region_size / (brw->urb.vs_size * 64);
+   int nr_vs_entries = handle_region_size / (vs_size * 64);
    if (nr_vs_entries > brw->urb.max_vs_entries)
       nr_vs_entries = brw->urb.max_vs_entries;
 
@@ -67,53 +88,39 @@ prepare_urb(struct brw_context *brw)
    brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 8);
 
    /* URB Starting Addresses are specified in multiples of 8kB. */
-   brw->urb.vs_start = 2; /* skip over push constants */
-}
-
-static void
-upload_urb(struct brw_context *brw)
-{
-   struct intel_context *intel = &brw->intel;
+   brw->urb.vs_start = push_size_kB / 8; /* skip over push constants */
 
    assert(brw->urb.nr_vs_entries % 8 == 0);
    assert(brw->urb.nr_gs_entries % 8 == 0);
    /* GS requirement */
    assert(!brw->gs.prog_active);
 
-   BEGIN_BATCH(2);
-   OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2));
-   OUT_BATCH(8);
-   ADVANCE_BATCH();
-
-   BEGIN_BATCH(2);
-   OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2));
-   OUT_BATCH(8 | 8 << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
-   ADVANCE_BATCH();
+   gen7_emit_vs_workaround_flush(brw);
+   gen7_emit_urb_state(brw, brw->urb.nr_vs_entries, vs_size, brw->urb.vs_start);
+}
 
-   BEGIN_BATCH(2);
+void
+gen7_emit_urb_state(struct brw_context *brw, GLuint nr_vs_entries,
+                    GLuint vs_size, GLuint vs_start)
+{
+   BEGIN_BATCH(8);
    OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2));
-   OUT_BATCH(brw->urb.nr_vs_entries |
-             ((brw->urb.vs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
-            (brw->urb.vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
-   ADVANCE_BATCH();
+   OUT_BATCH(nr_vs_entries |
+             ((vs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
+             (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
 
    /* Allocate the GS, HS, and DS zero space - we don't use them. */
-   BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2));
    OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
-             (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
-   ADVANCE_BATCH();
+             (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
 
-   BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2));
    OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
-             (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
-   ADVANCE_BATCH();
+             (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
 
-   BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2));
    OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
-             (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+             (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
    ADVANCE_BATCH();
 }
 
@@ -123,6 +130,5 @@ const struct brw_tracked_state gen7_urb = {
       .brw = BRW_NEW_CONTEXT,
       .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG),
    },
-   .prepare = prepare_urb,
-   .emit = upload_urb,
+   .emit = gen7_upload_urb,
 };