i965/state: Don't use brw->state.dirty.brw

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_vs_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 6a7add8e562f7bd845496d2c43939931e92aa59a..278b3ec6d215cc5b93a902c133608c90852a8a5d 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -29,55 +29,84 @@
 #include "program/prog_statevars.h"
 #include "intel_batchbuffer.h"
 
-static void
-upload_vs_state(struct brw_context *brw)
+
+void
+gen7_upload_constant_state(struct brw_context *brw,
+                           const struct brw_stage_state *stage_state,
+                           bool active, unsigned opcode)
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
+   uint32_t mocs = brw->gen < 8 ? GEN7_MOCS_L3 : 0;
 
-   BEGIN_BATCH(2);
-   OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
-   OUT_BATCH(brw->vs.bind_bo_offset);
-   ADVANCE_BATCH();
+   /* Disable if the shader stage is inactive or there are no push constants. */
+   active = active && stage_state->push_const_size != 0;
 
-   if (brw->vs.push_const_size == 0) {
-      /* Disable the push constant buffers. */
-      BEGIN_BATCH(7);
-      OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
+   int dwords = brw->gen >= 8 ? 11 : 7;
+   BEGIN_BATCH(dwords);
+   OUT_BATCH(opcode << 16 | (dwords - 2));
+   OUT_BATCH(active ? stage_state->push_const_size : 0);
+   OUT_BATCH(0);
+   /* Pointer to the constant buffer.  Covered by the set of state flags
+    * from gen6_prepare_wm_contants
+    */
+   OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   if (brw->gen >= 8) {
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
-      ADVANCE_BATCH();
-   } else {
-      BEGIN_BATCH(7);
-      OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
-      OUT_BATCH(brw->vs.push_const_size);
-      OUT_BATCH(0);
-      /* Pointer to the VS constant buffer.  Covered by the set of
-       * state flags from gen6_prepare_wm_contants
-       */
-      OUT_BATCH(brw->vs.push_const_offset);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
       OUT_BATCH(0);
-      ADVANCE_BATCH();
    }
 
+   ADVANCE_BATCH();
+
+  /* On SKL+ the new constants don't take effect until the next corresponding
+   * 3DSTATE_BINDING_TABLE_POINTER_* command is parsed so we need to ensure
+   * that is sent
+   */
+   if (brw->gen >= 9)
+      brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
+}
+
+
+static void
+upload_vs_state(struct brw_context *brw)
+{
+   const struct brw_stage_state *stage_state = &brw->vs.base;
+   uint32_t floating_point_mode = 0;
+   const int max_threads_shift = brw->is_haswell ?
+      HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT;
+
+   if (!brw->is_haswell && !brw->is_baytrail)
+      gen7_emit_vs_workaround_flush(brw);
+
+   if (brw->vs.prog_data->base.base.use_alt_mode)
+      floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
+
    BEGIN_BATCH(6);
    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
-   OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-   OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
-            GEN6_VS_FLOATING_POINT_MODE_ALT |
-            (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
-   OUT_BATCH(0); /* scratch space base offset */
-   OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
-            (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
+   OUT_BATCH(stage_state->prog_offset);
+   OUT_BATCH(floating_point_mode |
+            ((ALIGN(stage_state->sampler_count, 4)/4) <<
+              GEN6_VS_SAMPLER_COUNT_SHIFT) |
+             ((brw->vs.prog_data->base.base.binding_table.size_bytes / 4) <<
+              GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
+
+   if (brw->vs.prog_data->base.base.total_scratch) {
+      OUT_RELOC(stage_state->scratch_bo,
+               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+               ffs(brw->vs.prog_data->base.base.total_scratch) - 11);
+   } else {
+      OUT_BATCH(0);
+   }
+
+   OUT_BATCH((brw->vs.prog_data->base.base.dispatch_grf_start_reg <<
+              GEN6_VS_DISPATCH_START_GRF_SHIFT) |
+            (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
             (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 
-   OUT_BATCH(((brw->vs_max_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
+   OUT_BATCH(((brw->max_vs_threads - 1) << max_threads_shift) |
             GEN6_VS_STATISTICS_ENABLE |
             GEN6_VS_ENABLE);
    ADVANCE_BATCH();
@@ -85,15 +114,10 @@ upload_vs_state(struct brw_context *brw)
 
 const struct brw_tracked_state gen7_vs_state = {
    .dirty = {
-      .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
-      .brw   = (BRW_NEW_CURBE_OFFSETS |
-                BRW_NEW_NR_VS_SURFACES |
-               BRW_NEW_URB_FENCE |
-               BRW_NEW_CONTEXT |
-               BRW_NEW_VERTEX_PROGRAM |
-               BRW_NEW_VS_BINDING_TABLE |
-               BRW_NEW_BATCH),
-      .cache = CACHE_NEW_VS_PROG
+      .mesa  = _NEW_TRANSFORM,
+      .brw   = BRW_NEW_BATCH |
+               BRW_NEW_CONTEXT |
+               BRW_NEW_VS_PROG_DATA,
    },
    .emit = upload_vs_state,
 };