i965: Remove never used RSR and RSL opcodes.

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_vs_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index ce584f675f6e33ca7a8e773c266c568478bb1aff..6e72e8f29b9682d2e1783920cd4d5e4af9758ec4 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -33,6 +33,7 @@ static void
 upload_vs_state(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->ctx;
+   const struct brw_stage_state *stage_state = &brw->vs.base;
    uint32_t floating_point_mode = 0;
    const int max_threads_shift = brw->is_haswell ?
       HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT;
@@ -42,16 +43,16 @@ upload_vs_state(struct brw_context *brw)
    /* BRW_NEW_VS_BINDING_TABLE */
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
-   OUT_BATCH(brw->vs.bind_bo_offset);
+   OUT_BATCH(stage_state->bind_bo_offset);
    ADVANCE_BATCH();
 
    /* CACHE_NEW_SAMPLER */
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2));
-   OUT_BATCH(brw->vs.sampler_offset);
+   OUT_BATCH(stage_state->sampler_offset);
    ADVANCE_BATCH();
 
-   if (brw->vs.push_const_size == 0) {
+   if (stage_state->push_const_size == 0) {
       /* Disable the push constant buffers. */
       BEGIN_BATCH(7);
       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
@@ -65,12 +66,12 @@ upload_vs_state(struct brw_context *brw)
    } else {
       BEGIN_BATCH(7);
       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
-      OUT_BATCH(brw->vs.push_const_size);
+      OUT_BATCH(stage_state->push_const_size);
       OUT_BATCH(0);
       /* Pointer to the VS constant buffer.  Covered by the set of
        * state flags from gen6_prepare_wm_contants
        */
-      OUT_BATCH(brw->vs.push_const_offset | GEN7_MOCS_L3);
+      OUT_BATCH(stage_state->push_const_offset | GEN7_MOCS_L3);
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
@@ -85,12 +86,13 @@ upload_vs_state(struct brw_context *brw)
 
    BEGIN_BATCH(6);
    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
-   OUT_BATCH(brw->vs.prog_offset);
+   OUT_BATCH(stage_state->prog_offset);
    OUT_BATCH(floating_point_mode |
-            ((ALIGN(brw->vs.sampler_count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT));
+            ((ALIGN(stage_state->sampler_count, 4)/4) <<
+              GEN6_VS_SAMPLER_COUNT_SHIFT));
 
    if (brw->vs.prog_data->base.total_scratch) {
-      OUT_RELOC(brw->vs.scratch_bo,
+      OUT_RELOC(stage_state->scratch_bo,
                I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
                ffs(brw->vs.prog_data->base.total_scratch) - 11);
    } else {
@@ -114,7 +116,8 @@ const struct brw_tracked_state gen7_vs_state = {
       .brw   = (BRW_NEW_CONTEXT |
                BRW_NEW_VERTEX_PROGRAM |
                BRW_NEW_VS_BINDING_TABLE |
-               BRW_NEW_BATCH),
+               BRW_NEW_BATCH |
+                BRW_NEW_PUSH_CONSTANT_ALLOCATION),
       .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
    },
    .emit = upload_vs_state,