i965: Set Broadwell MOCS values everywhere it's possible.

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_vs_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 462db5bf1944a84287b07e1d92636237253167d6..b5fc871cfe10fe869a1f7d12056bd019334b5e6d 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -29,21 +29,16 @@
 #include "program/prog_statevars.h"
 #include "intel_batchbuffer.h"
 
-static void
-upload_vs_state(struct brw_context *brw)
-{
-   struct intel_context *intel = &brw->intel;
-   uint32_t floating_point_mode = 0;
-
-   BEGIN_BATCH(2);
-   OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
-   OUT_BATCH(brw->vs.bind_bo_offset);
-   ADVANCE_BATCH();
 
-   if (brw->vs.push_const_size == 0) {
+void
+gen7_upload_constant_state(struct brw_context *brw,
+                           const struct brw_stage_state *stage_state,
+                           bool active, unsigned opcode)
+{
+   if (!active || stage_state->push_const_size == 0) {
       /* Disable the push constant buffers. */
       BEGIN_BATCH(7);
-      OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
+      OUT_BATCH(opcode << 16 | (7 - 2));
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
@@ -53,43 +48,71 @@ upload_vs_state(struct brw_context *brw)
       ADVANCE_BATCH();
    } else {
       BEGIN_BATCH(7);
-      OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
-      OUT_BATCH(brw->vs.push_const_size);
+      OUT_BATCH(opcode << 16 | (7 - 2));
+      OUT_BATCH(stage_state->push_const_size);
       OUT_BATCH(0);
-      /* Pointer to the VS constant buffer.  Covered by the set of
-       * state flags from gen6_prepare_wm_contants
+      /* Pointer to the constant buffer.  Covered by the set of state flags
+       * from gen6_prepare_wm_contants
        */
-      OUT_BATCH(brw->vs.push_const_offset);
+      OUT_BATCH(stage_state->push_const_offset | GEN7_MOCS_L3);
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
       ADVANCE_BATCH();
    }
+}
+
+
+static void
+upload_vs_state(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->ctx;
+   const struct brw_stage_state *stage_state = &brw->vs.base;
+   uint32_t floating_point_mode = 0;
+   const int max_threads_shift = brw->is_haswell ?
+      HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT;
+
+   if (!brw->is_haswell)
+      gen7_emit_vs_workaround_flush(brw);
+
+   /* CACHE_NEW_SAMPLER */
+   BEGIN_BATCH(2);
+   OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2));
+   OUT_BATCH(stage_state->sampler_offset);
+   ADVANCE_BATCH();
+
+   gen7_upload_constant_state(brw, stage_state, true /* active */,
+                              _3DSTATE_CONSTANT_VS);
 
    /* Use ALT floating point mode for ARB vertex programs, because they
     * require 0^0 == 1.
     */
-   if (intel->ctx.Shader.CurrentVertexProgram == NULL)
+   if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX] == NULL)
       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
 
    BEGIN_BATCH(6);
    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
-   OUT_BATCH(brw->vs.prog_offset);
-   OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) | floating_point_mode);
+   OUT_BATCH(stage_state->prog_offset);
+   OUT_BATCH(floating_point_mode |
+            ((ALIGN(stage_state->sampler_count, 4)/4) <<
+              GEN6_VS_SAMPLER_COUNT_SHIFT) |
+             ((brw->vs.prog_data->base.base.binding_table.size_bytes / 4) <<
+              GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 
-   if (brw->vs.prog_data->total_scratch) {
-      OUT_RELOC(brw->vs.scratch_bo,
+   if (brw->vs.prog_data->base.total_scratch) {
+      OUT_RELOC(stage_state->scratch_bo,
                I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-               ffs(brw->vs.prog_data->total_scratch) - 11);
+               ffs(brw->vs.prog_data->base.total_scratch) - 11);
    } else {
       OUT_BATCH(0);
    }
 
-   OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
-            (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
+   OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg <<
+              GEN6_VS_DISPATCH_START_GRF_SHIFT) |
+            (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
             (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 
-   OUT_BATCH(((brw->max_vs_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
+   OUT_BATCH(((brw->max_vs_threads - 1) << max_threads_shift) |
             GEN6_VS_STATISTICS_ENABLE |
             GEN6_VS_ENABLE);
    ADVANCE_BATCH();
@@ -98,13 +121,12 @@ upload_vs_state(struct brw_context *brw)
 const struct brw_tracked_state gen7_vs_state = {
    .dirty = {
       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
-      .brw   = (BRW_NEW_CURBE_OFFSETS |
-               BRW_NEW_URB_FENCE |
-               BRW_NEW_CONTEXT |
+      .brw   = (BRW_NEW_CONTEXT |
                BRW_NEW_VERTEX_PROGRAM |
                BRW_NEW_VS_BINDING_TABLE |
-               BRW_NEW_BATCH),
-      .cache = CACHE_NEW_VS_PROG
+               BRW_NEW_BATCH |
+                BRW_NEW_PUSH_CONSTANT_ALLOCATION),
+      .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
    },
    .emit = upload_vs_state,
 };