i965: Alphabetize brw_tracked_state flags and use a consistent style.
[mesa.git] / src / mesa / drivers / dri / i965 / gen7_vs_state.c
index 6b1f6807950d5fc3f2dbf72ac8c244f7feb7dcb2..e9144d9cd33adb3b4b4d00898e4b0c7f13830e70 100644 (file)
@@ -35,31 +35,31 @@ gen7_upload_constant_state(struct brw_context *brw,
                            const struct brw_stage_state *stage_state,
                            bool active, unsigned opcode)
 {
-   if (!active || stage_state->push_const_size == 0) {
-      /* Disable the push constant buffers. */
-      BEGIN_BATCH(7);
-      OUT_BATCH(opcode << 16 | (7 - 2));
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-   } else {
-      BEGIN_BATCH(7);
-      OUT_BATCH(opcode << 16 | (7 - 2));
-      OUT_BATCH(stage_state->push_const_size);
+   uint32_t mocs = brw->gen < 8 ? GEN7_MOCS_L3 : 0;
+
+   /* Disable if the shader stage is inactive or there are no push constants. */
+   active = active && stage_state->push_const_size != 0;
+
+   int dwords = brw->gen >= 8 ? 11 : 7;
+   BEGIN_BATCH(dwords);
+   OUT_BATCH(opcode << 16 | (dwords - 2));
+   OUT_BATCH(active ? stage_state->push_const_size : 0);
+   OUT_BATCH(0);
+   /* Pointer to the constant buffer.  Covered by the set of state flags
+    * from gen6_prepare_wm_contants
+    */
+   OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   if (brw->gen >= 8) {
       OUT_BATCH(0);
-      /* Pointer to the constant buffer.  Covered by the set of state flags
-       * from gen6_prepare_wm_contants
-       */
-      OUT_BATCH(stage_state->push_const_offset | GEN7_MOCS_L3);
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
-      ADVANCE_BATCH();
    }
+
+   ADVANCE_BATCH();
 }
 
 
@@ -72,12 +72,9 @@ upload_vs_state(struct brw_context *brw)
    const int max_threads_shift = brw->is_haswell ?
       HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT;
 
-   if (!brw->is_haswell)
+   if (!brw->is_haswell && !brw->is_baytrail)
       gen7_emit_vs_workaround_flush(brw);
 
-   gen7_upload_constant_state(brw, stage_state, true /* active */,
-                              _3DSTATE_CONSTANT_VS);
-
    /* Use ALT floating point mode for ARB vertex programs, because they
     * require 0^0 == 1.
     */
@@ -93,15 +90,15 @@ upload_vs_state(struct brw_context *brw)
              ((brw->vs.prog_data->base.base.binding_table.size_bytes / 4) <<
               GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 
-   if (brw->vs.prog_data->base.total_scratch) {
+   if (brw->vs.prog_data->base.base.total_scratch) {
       OUT_RELOC(stage_state->scratch_bo,
                I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-               ffs(brw->vs.prog_data->base.total_scratch) - 11);
+               ffs(brw->vs.prog_data->base.base.total_scratch) - 11);
    } else {
       OUT_BATCH(0);
    }
 
-   OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg <<
+   OUT_BATCH((brw->vs.prog_data->base.base.dispatch_grf_start_reg <<
               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
             (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
             (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
@@ -114,12 +111,10 @@ upload_vs_state(struct brw_context *brw)
 
 const struct brw_tracked_state gen7_vs_state = {
    .dirty = {
-      .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
-      .brw   = (BRW_NEW_CONTEXT |
-               BRW_NEW_VERTEX_PROGRAM |
-               BRW_NEW_VS_BINDING_TABLE |
-               BRW_NEW_BATCH |
-                BRW_NEW_PUSH_CONSTANT_ALLOCATION),
+      .mesa  = _NEW_TRANSFORM,
+      .brw   = BRW_NEW_BATCH |
+               BRW_NEW_CONTEXT |
+               BRW_NEW_VERTEX_PROGRAM,
       .cache = CACHE_NEW_VS_PROG
    },
    .emit = upload_vs_state,