#include "brw_defines.h"
#include "brw_util.h"
#include "brw_wm.h"
+#include "program/program.h"
#include "program/prog_parameter.h"
#include "program/prog_statevars.h"
#include "intel_batchbuffer.h"
-static void
-gen7_prepare_wm_constants(struct brw_context *brw)
-{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
- /* BRW_NEW_FRAGMENT_PROGRAM */
- const struct brw_fragment_program *fp =
- brw_fragment_program_const(brw->fragment_program);
-
- /* Updates the ParameterValues[i] pointers for all parameters of the
- * basic type of PROGRAM_STATE_VAR.
- */
- /* XXX: Should this happen somewhere before to get our state flag set? */
- _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
-
- /* CACHE_NEW_WM_PROG */
- if (brw->wm.prog_data->nr_params != 0) {
- float *constants;
- unsigned int i;
-
- constants = brw_state_batch(brw,
- brw->wm.prog_data->nr_params *
- sizeof(float),
- 32, &brw->wm.push_const_offset);
-
- for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
- constants[i] = convert_param(brw->wm.prog_data->param_convert[i],
- *brw->wm.prog_data->param[i]);
- }
-
- if (0) {
- printf("WM constants:\n");
- for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
- if ((i & 7) == 0)
- printf("g%d: ", brw->wm.prog_data->first_curbe_grf + i / 8);
- printf("%8f ", constants[i]);
- if ((i & 7) == 7)
- printf("\n");
- }
- if ((i & 7) != 0)
- printf("\n");
- printf("\n");
- }
- }
-}
-
-const struct brw_tracked_state gen7_wm_constants = {
- .dirty = {
- .mesa = _NEW_PROGRAM_CONSTANTS,
- .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
- .cache = CACHE_NEW_WM_PROG,
- },
- .prepare = gen7_prepare_wm_constants,
-};
-
static void
upload_wm_state(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw->fragment_program);
bool writes_depth = false;
- uint32_t dw1;
+ uint32_t dw1, dw2;
- dw1 = 0;
+ /* _NEW_BUFFERS */
+ bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
+
+ dw1 = dw2 = 0;
dw1 |= GEN7_WM_STATISTICS_ENABLE;
dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
/* BRW_NEW_FRAGMENT_PROGRAM */
- if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
+ if (fp->program.Base.InputsRead & VARYING_BIT_POS)
dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
- writes_depth = true;
- dw1 |= GEN7_WM_PSCDEPTH_ON;
+ writes_depth = fp->program.FragDepthLayout != FRAG_DEPTH_LAYOUT_UNCHANGED;
+
+ switch (fp->program.FragDepthLayout) {
+ case FRAG_DEPTH_LAYOUT_NONE:
+ case FRAG_DEPTH_LAYOUT_ANY:
+ dw1 |= GEN7_WM_PSCDEPTH_ON;
+ break;
+ case FRAG_DEPTH_LAYOUT_GREATER:
+ dw1 |= GEN7_WM_PSCDEPTH_ON_GE;
+ break;
+ case FRAG_DEPTH_LAYOUT_LESS:
+ dw1 |= GEN7_WM_PSCDEPTH_ON_LE;
+ break;
+ case FRAG_DEPTH_LAYOUT_UNCHANGED:
+ break;
+ }
}
+ /* CACHE_NEW_WM_PROG */
+ dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
+ GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
- /* _NEW_COLOR */
- if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
+ /* _NEW_COLOR, _NEW_MULTISAMPLE */
+ /* Enable if the pixel shader kernel generates and outputs oMask.
+ */
+ if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||
+ ctx->Multisample.SampleAlphaToCoverage ||
+ brw->wm.prog_data->uses_omask) {
dw1 |= GEN7_WM_KILL_ENABLE;
+ }
- /* _NEW_BUFFERS */
+ /* _NEW_BUFFERS | _NEW_COLOR */
if (brw_color_buffer_write_enabled(brw) || writes_depth ||
dw1 & GEN7_WM_KILL_ENABLE) {
dw1 |= GEN7_WM_DISPATCH_ENABLE;
}
+ if (multisampled_fbo) {
+ /* _NEW_MULTISAMPLE */
+ if (ctx->Multisample.Enabled)
+ dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
+ else
+ dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
+
+ if (_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false) > 1)
+ dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
+ else
+ dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
+ } else {
+ dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
+ dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
+ }
- dw1 |= GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
+ if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
+ dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK;
+ }
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
OUT_BATCH(dw1);
- OUT_BATCH(0);
+ OUT_BATCH(dw2);
ADVANCE_BATCH();
}
const struct brw_tracked_state gen7_wm_state = {
.dirty = {
.mesa = (_NEW_LINE | _NEW_POLYGON |
- _NEW_COLOR | _NEW_BUFFERS),
+ _NEW_COLOR | _NEW_BUFFERS |
+ _NEW_MULTISAMPLE),
.brw = (BRW_NEW_FRAGMENT_PROGRAM |
- BRW_NEW_URB_FENCE |
BRW_NEW_BATCH),
- .cache = 0,
+ .cache = CACHE_NEW_WM_PROG,
},
.emit = upload_wm_state,
};
static void
upload_ps_state(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
- uint32_t dw2, dw4, dw5;
+ struct gl_context *ctx = &brw->ctx;
+ uint32_t dw2, dw4, dw5, ksp0, ksp2;
+ const int max_threads_shift = brw->is_haswell ?
+ HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
- BEGIN_BATCH(2);
- OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
- OUT_BATCH(brw->wm.bind_bo_offset);
- ADVANCE_BATCH();
+ dw2 = dw4 = dw5 = ksp2 = 0;
- /* CACHE_NEW_SAMPLER */
- BEGIN_BATCH(2);
- OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
- OUT_BATCH(brw->wm.sampler_offset);
- ADVANCE_BATCH();
+ dw2 |=
+ (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
/* CACHE_NEW_WM_PROG */
- if (brw->wm.prog_data->nr_params == 0) {
- /* Disable the push constant buffers. */
- BEGIN_BATCH(7);
- OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
- } else {
- BEGIN_BATCH(7);
- OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
+ dw2 |= ((brw->wm.prog_data->base.binding_table.size_bytes / 4) <<
+ GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
- OUT_BATCH(ALIGN(brw->wm.prog_data->nr_params,
- brw->wm.prog_data->dispatch_width) / 8);
- OUT_BATCH(0);
- /* Pointer to the WM constant buffer. Covered by the set of
- * state flags from gen7_prepare_wm_constants
- */
- OUT_BATCH(brw->wm.push_const_offset);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
- }
+ /* Use ALT floating point mode for ARB fragment programs, because they
+ * require 0^0 == 1. Even though _CurrentFragmentProgram is used for
+ * rendering, CurrentProgram[MESA_SHADER_FRAGMENT] is used for this check
+ * to differentiate between the GLSL and non-GLSL cases.
+ */
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ if (ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
+ dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
- dw2 = dw4 = dw5 = 0;
+ /* Haswell requires the sample mask to be set in this packet as well as
+ * in 3DSTATE_SAMPLE_MASK; the values should match. */
+ /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
+ if (brw->is_haswell)
+ dw4 |= SET_FIELD(gen6_determine_sample_mask(brw), HSW_PS_SAMPLE_MASK);
- dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
+ dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
- /* BRW_NEW_NR_WM_SURFACES */
- dw2 |= brw->wm.nr_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT;
+ /* CACHE_NEW_WM_PROG */
+ if (brw->wm.prog_data->base.nr_params > 0)
+ dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
- /* OpenGL non-ieee floating point mode */
- dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
+ /* From the IVB PRM, volume 2 part 1, page 287:
+ * "This bit is inserted in the PS payload header and made available to
+ * the DataPort (either via the message header or via header bypass) to
+ * indicate that oMask data (one or two phases) is included in Render
+ * Target Write messages. If present, the oMask data is used to mask off
+ * samples."
+ */
+ if (brw->wm.prog_data->uses_omask)
+ dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;
+
+ /* From the IVB PRM, volume 2 part 1, page 287:
+ * "If the PS kernel does not need the Position XY Offsets to
+ * compute a Position Value, then this field should be programmed
+ * to POSOFFSET_NONE."
+ * "SW Recommendation: If the PS kernel needs the Position Offsets
+ * to compute a Position XY value, this field should match Position
+ * ZW Interpolation Mode to ensure a consistent position.xyzw
+ * computation."
+ * We only require XY sample offsets. So, this recommendation doesn't
+ * look useful at the moment. We might need this in future.
+ */
+ if (brw->wm.prog_data->uses_pos_offset)
+ dw4 |= GEN7_PS_POSOFFSET_SAMPLE;
+ else
+ dw4 |= GEN7_PS_POSOFFSET_NONE;
- /* CACHE_NEW_SAMPLER */
- dw4 |= (brw->wm_max_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT;
+ /* CACHE_NEW_WM_PROG | _NEW_COLOR
+ *
+ * The hardware wedges if you have this bit set but don't turn on any dual
+ * source blend factors.
+ */
+ if (brw->wm.prog_data->dual_src_blend &&
+ (ctx->Color.BlendEnabled & 1) &&
+ ctx->Color.Blend[0]._UsesDualSrc) {
+ dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
+ }
/* CACHE_NEW_WM_PROG */
- if (brw->wm.prog_data->nr_params > 0)
- dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
-
- /* BRW_NEW_FRAGMENT_PROGRAM */
- if (brw->fragment_program->Base.InputsRead != 0)
+ if (brw->wm.prog_data->num_varying_inputs != 0)
dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
- if (brw->wm.prog_data->dispatch_width == 8)
- dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
- else
+ /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
+ * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
+ * is successfully compiled. In majority of the cases that bring us
+ * better performance than 'SIMD8 only' dispatch.
+ */
+ int min_inv_per_frag =
+ _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
+ assert(min_inv_per_frag >= 1);
+
+ if (brw->wm.prog_data->prog_offset_16 || brw->wm.prog_data->no_8) {
dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
+ if (!brw->wm.prog_data->no_8 && min_inv_per_frag == 1) {
+ dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
+ dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
+ GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+ dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
+ GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
+ ksp0 = brw->wm.base.prog_offset;
+ ksp2 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
+ } else {
+ dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
+ GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+ ksp0 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
+ }
+ }
+ else {
+ dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
+ dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
+ GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+ ksp0 = brw->wm.base.prog_offset;
+ }
- /* BRW_NEW_CURBE_OFFSETS */
- dw5 |= (brw->wm.prog_data->first_curbe_grf <<
- GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+ dw4 |= brw->wm.fast_clear_op;
BEGIN_BATCH(8);
OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
- OUT_BATCH(brw->wm.prog_offset);
+ OUT_BATCH(ksp0);
OUT_BATCH(dw2);
- OUT_BATCH(0); /* scratch space base offset */
+ if (brw->wm.prog_data->total_scratch) {
+ OUT_RELOC(brw->wm.base.scratch_bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ ffs(brw->wm.prog_data->total_scratch) - 11);
+ } else {
+ OUT_BATCH(0);
+ }
OUT_BATCH(dw4);
OUT_BATCH(dw5);
OUT_BATCH(0); /* kernel 1 pointer */
- OUT_BATCH(brw->wm.prog_offset + brw->wm.prog_data->prog_offset_16);
+ OUT_BATCH(ksp2);
ADVANCE_BATCH();
}
const struct brw_tracked_state gen7_ps_state = {
.dirty = {
- .mesa = _NEW_PROGRAM_CONSTANTS,
- .brw = (BRW_NEW_CURBE_OFFSETS |
- BRW_NEW_FRAGMENT_PROGRAM |
- BRW_NEW_NR_WM_SURFACES |
- BRW_NEW_PS_BINDING_TABLE |
- BRW_NEW_URB_FENCE |
- BRW_NEW_BATCH),
- .cache = (CACHE_NEW_SAMPLER |
- CACHE_NEW_WM_PROG)
+ .mesa = (_NEW_COLOR |
+ _NEW_BUFFERS |
+ _NEW_MULTISAMPLE),
+ .brw = (BRW_NEW_FRAGMENT_PROGRAM |
+ BRW_NEW_BATCH),
+ .cache = (CACHE_NEW_WM_PROG)
},
.emit = upload_ps_state,
};
projects / mesa.git / blobdiff