i965/gen8: Add instruction compaction tables.

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_wm_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 2b95ef1ffd2f716f45430f9135c45a048ba498e4..278cf17964c7bdedabf2482bb435e29a8f351b8f 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -139,14 +139,11 @@ static void
 upload_ps_state(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->ctx;
-   uint32_t dw2, dw4, dw5;
+   uint32_t dw2, dw4, dw5, ksp0, ksp2;
    const int max_threads_shift = brw->is_haswell ?
       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 
-   /* CACHE_NEW_WM_PROG */
-   gen7_upload_constant_state(brw, &brw->wm.base, true, _3DSTATE_CONSTANT_PS);
-
-   dw2 = dw4 = dw5 = 0;
+   dw2 = dw4 = dw5 = ksp2 = 0;
 
    dw2 |=
       (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
@@ -226,30 +223,34 @@ upload_ps_state(struct brw_context *brw)
       _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
    assert(min_inv_per_frag >= 1);
 
-   if (brw->wm.prog_data->prog_offset_16) {
+   if (brw->wm.prog_data->prog_offset_16 || brw->wm.prog_data->no_8) {
       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
-      if (min_inv_per_frag == 1) {
+      if (!brw->wm.prog_data->no_8 && min_inv_per_frag == 1) {
          dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
-         dw5 |= (brw->wm.prog_data->first_curbe_grf <<
+         dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
-         dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+         dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
-      } else
-         dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+         ksp0 = brw->wm.base.prog_offset;
+         ksp2 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
+      } else {
+         dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+         ksp0 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
+      }
    }
    else {
       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
-      dw5 |= (brw->wm.prog_data->first_curbe_grf <<
+      dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+      ksp0 = brw->wm.base.prog_offset;
    }
 
+   dw4 |= brw->wm.fast_clear_op;
+
    BEGIN_BATCH(8);
    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
-   if (brw->wm.prog_data->prog_offset_16 && min_inv_per_frag > 1)
-      OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
-   else
-      OUT_BATCH(brw->wm.base.prog_offset);
+   OUT_BATCH(ksp0);
    OUT_BATCH(dw2);
    if (brw->wm.prog_data->total_scratch) {
       OUT_RELOC(brw->wm.base.scratch_bo,
@@ -261,20 +262,17 @@ upload_ps_state(struct brw_context *brw)
    OUT_BATCH(dw4);
    OUT_BATCH(dw5);
    OUT_BATCH(0); /* kernel 1 pointer */
-   OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
+   OUT_BATCH(ksp2);
    ADVANCE_BATCH();
 }
 
 const struct brw_tracked_state gen7_ps_state = {
    .dirty = {
-      .mesa  = (_NEW_PROGRAM_CONSTANTS |
-               _NEW_COLOR |
+      .mesa  = (_NEW_COLOR |
                 _NEW_BUFFERS |
                 _NEW_MULTISAMPLE),
       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
-               BRW_NEW_PS_BINDING_TABLE |
-               BRW_NEW_BATCH |
-                BRW_NEW_PUSH_CONSTANT_ALLOCATION),
+                BRW_NEW_BATCH),
       .cache = (CACHE_NEW_WM_PROG)
    },
    .emit = upload_ps_state,