i965: Update max VS/PS threads shift offsets for Haswell.
[mesa.git] / src / mesa / drivers / dri / i965 / gen7_wm_state.c
index b63776f7a55de2ab052052bdf36cddc5c6060f32..773598f2c488976c91b8ec595452504032af3849 100644 (file)
 #include "program/prog_statevars.h"
 #include "intel_batchbuffer.h"
 
-static void
-gen7_prepare_wm_constants(struct brw_context *brw)
-{
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
-   /* BRW_NEW_FRAGMENT_PROGRAM */
-   const struct brw_fragment_program *fp =
-      brw_fragment_program_const(brw->fragment_program);
-
-   /* Updates the ParameterValues[i] pointers for all parameters of the
-    * basic type of PROGRAM_STATE_VAR.
-    */
-   /* XXX: Should this happen somewhere before to get our state flag set? */
-   _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
-
-   /* CACHE_NEW_WM_PROG */
-   if (brw->wm.prog_data->nr_params != 0) {
-      float *constants;
-      unsigned int i;
-
-      constants = brw_state_batch(brw, AUB_TRACE_WM_CONSTANTS,
-                                 brw->wm.prog_data->nr_params *
-                                 sizeof(float),
-                                 32, &brw->wm.push_const_offset);
-
-      for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
-        constants[i] = convert_param(brw->wm.prog_data->param_convert[i],
-                                     brw->wm.prog_data->param[i]);
-      }
-
-      if (0) {
-        printf("WM constants:\n");
-        for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
-           if ((i & 7) == 0)
-              printf("g%d: ", brw->wm.prog_data->first_curbe_grf + i / 8);
-           printf("%8f ", constants[i]);
-           if ((i & 7) == 7)
-              printf("\n");
-        }
-        if ((i & 7) != 0)
-           printf("\n");
-        printf("\n");
-      }
-   }
-}
-
-const struct brw_tracked_state gen7_wm_constants = {
-   .dirty = {
-      .mesa  = _NEW_PROGRAM_CONSTANTS,
-      .brw   = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
-      .cache = CACHE_NEW_WM_PROG,
-   },
-   .prepare = gen7_prepare_wm_constants,
-};
-
 static void
 upload_wm_state(struct brw_context *brw)
 {
@@ -110,12 +55,15 @@ upload_wm_state(struct brw_context *brw)
       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 
    /* BRW_NEW_FRAGMENT_PROGRAM */
-   if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
+   if (fp->program.Base.InputsRead & FRAG_BIT_WPOS)
       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
       writes_depth = true;
       dw1 |= GEN7_WM_PSCDEPTH_ON;
    }
+   /* CACHE_NEW_WM_PROG */
+   dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
+      GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 
    /* _NEW_COLOR */
    if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
@@ -127,8 +75,6 @@ upload_wm_state(struct brw_context *brw)
       dw1 |= GEN7_WM_DISPATCH_ENABLE;
    }
 
-   dw1 |= GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
-
    BEGIN_BATCH(3);
    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
    OUT_BATCH(dw1);
@@ -141,9 +87,8 @@ const struct brw_tracked_state gen7_wm_state = {
       .mesa  = (_NEW_LINE | _NEW_POLYGON |
                _NEW_COLOR | _NEW_BUFFERS),
       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
-               BRW_NEW_URB_FENCE |
                BRW_NEW_BATCH),
-      .cache = 0,
+      .cache = CACHE_NEW_WM_PROG,
    },
    .emit = upload_wm_state,
 };
@@ -153,7 +98,10 @@ upload_ps_state(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
    uint32_t dw2, dw4, dw5;
+   const int max_threads_shift = brw->intel.is_haswell ?
+      HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 
+   /* BRW_NEW_PS_BINDING_TABLE */
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
    OUT_BATCH(brw->wm.bind_bo_offset);
@@ -162,7 +110,7 @@ upload_ps_state(struct brw_context *brw)
    /* CACHE_NEW_SAMPLER */
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
-   OUT_BATCH(brw->wm.sampler_offset);
+   OUT_BATCH(brw->sampler.offset);
    ADVANCE_BATCH();
 
    /* CACHE_NEW_WM_PROG */
@@ -185,7 +133,7 @@ upload_ps_state(struct brw_context *brw)
                      brw->wm.prog_data->dispatch_width) / 8);
       OUT_BATCH(0);
       /* Pointer to the WM constant buffer.  Covered by the set of
-       * state flags from gen7_prepare_wm_constants
+       * state flags from gen6_upload_wm_push_constants.
        */
       OUT_BATCH(brw->wm.push_const_offset);
       OUT_BATCH(0);
@@ -196,16 +144,18 @@ upload_ps_state(struct brw_context *brw)
 
    dw2 = dw4 = dw5 = 0;
 
-   dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
-
-   /* BRW_NEW_NR_WM_SURFACES */
-   dw2 |= brw->wm.nr_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT;
+   /* CACHE_NEW_SAMPLER */
+   dw2 |= (ALIGN(brw->sampler.count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 
-   /* OpenGL non-ieee floating point mode */
-   dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
+   /* Use ALT floating point mode for ARB fragment programs, because they
+    * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
+    * rendering, CurrentFragmentProgram is used for this check to
+    * differentiate between the GLSL and non-GLSL cases.
+    */
+   if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
+      dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 
-   /* CACHE_NEW_SAMPLER */
-   dw4 |= (brw->wm_max_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT;
+   dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 
    /* CACHE_NEW_WM_PROG */
    if (brw->wm.prog_data->nr_params > 0)
@@ -215,14 +165,18 @@ upload_ps_state(struct brw_context *brw)
    if (brw->fragment_program->Base.InputsRead != 0)
       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 
-   if (brw->wm.prog_data->dispatch_width == 8)
+   if (brw->wm.prog_data->dispatch_width == 8) {
       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
-   else
+      if (brw->wm.prog_data->prog_offset_16)
+        dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
+   } else {
       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
+   }
 
-   /* BRW_NEW_CURBE_OFFSETS */
    dw5 |= (brw->wm.prog_data->first_curbe_grf <<
           GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+   dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+          GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 
    BEGIN_BATCH(8);
    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
@@ -245,11 +199,8 @@ upload_ps_state(struct brw_context *brw)
 const struct brw_tracked_state gen7_ps_state = {
    .dirty = {
       .mesa  = _NEW_PROGRAM_CONSTANTS,
-      .brw   = (BRW_NEW_CURBE_OFFSETS |
-               BRW_NEW_FRAGMENT_PROGRAM |
-                BRW_NEW_NR_WM_SURFACES |
+      .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
                BRW_NEW_PS_BINDING_TABLE |
-               BRW_NEW_URB_FENCE |
                BRW_NEW_BATCH),
       .cache = (CACHE_NEW_SAMPLER |
                CACHE_NEW_WM_PROG)