i965: Update max VS/PS threads shift offsets for Haswell.

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_wm_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index f63cf54cdb42ac149054abdc38aad9f5127ea82c..773598f2c488976c91b8ec595452504032af3849 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -41,9 +41,6 @@ upload_wm_state(struct brw_context *brw)
    bool writes_depth = false;
    uint32_t dw1;
 
-   /* _NEW_LIGHT */
-   bool flat_shade = (ctx->Light.ShadeModel == GL_FLAT);
-
    dw1 = 0;
    dw1 |= GEN7_WM_STATISTICS_ENABLE;
    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
@@ -64,7 +61,8 @@ upload_wm_state(struct brw_context *brw)
       writes_depth = true;
       dw1 |= GEN7_WM_PSCDEPTH_ON;
    }
-   dw1 |= brw_compute_barycentric_interp_modes(flat_shade, &fp->program) <<
+   /* CACHE_NEW_WM_PROG */
+   dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 
    /* _NEW_COLOR */
@@ -86,12 +84,11 @@ upload_wm_state(struct brw_context *brw)
 
 const struct brw_tracked_state gen7_wm_state = {
    .dirty = {
-      .mesa  = (_NEW_LINE | _NEW_LIGHT | _NEW_POLYGON |
+      .mesa  = (_NEW_LINE | _NEW_POLYGON |
                _NEW_COLOR | _NEW_BUFFERS),
       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
-               BRW_NEW_URB_FENCE |
                BRW_NEW_BATCH),
-      .cache = 0,
+      .cache = CACHE_NEW_WM_PROG,
    },
    .emit = upload_wm_state,
 };
@@ -101,10 +98,13 @@ upload_ps_state(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
    uint32_t dw2, dw4, dw5;
+   const int max_threads_shift = brw->intel.is_haswell ?
+      HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 
+   /* BRW_NEW_PS_BINDING_TABLE */
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
-   OUT_BATCH(brw->bind.bo_offset);
+   OUT_BATCH(brw->wm.bind_bo_offset);
    ADVANCE_BATCH();
 
    /* CACHE_NEW_SAMPLER */
@@ -133,7 +133,7 @@ upload_ps_state(struct brw_context *brw)
                      brw->wm.prog_data->dispatch_width) / 8);
       OUT_BATCH(0);
       /* Pointer to the WM constant buffer.  Covered by the set of
-       * state flags from gen7_prepare_wm_constants
+       * state flags from gen6_upload_wm_push_constants.
        */
       OUT_BATCH(brw->wm.push_const_offset);
       OUT_BATCH(0);
@@ -144,16 +144,18 @@ upload_ps_state(struct brw_context *brw)
 
    dw2 = dw4 = dw5 = 0;
 
+   /* CACHE_NEW_SAMPLER */
    dw2 |= (ALIGN(brw->sampler.count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 
    /* Use ALT floating point mode for ARB fragment programs, because they
-    * require 0^0 == 1.
+    * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
+    * rendering, CurrentFragmentProgram is used for this check to
+    * differentiate between the GLSL and non-GLSL cases.
     */
    if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 
-   /* CACHE_NEW_SAMPLER */
-   dw4 |= (brw->max_wm_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT;
+   dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 
    /* CACHE_NEW_WM_PROG */
    if (brw->wm.prog_data->nr_params > 0)
@@ -171,7 +173,6 @@ upload_ps_state(struct brw_context *brw)
       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
    }
 
-   /* BRW_NEW_CURBE_OFFSETS */
    dw5 |= (brw->wm.prog_data->first_curbe_grf <<
           GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
    dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
@@ -198,10 +199,8 @@ upload_ps_state(struct brw_context *brw)
 const struct brw_tracked_state gen7_ps_state = {
    .dirty = {
       .mesa  = _NEW_PROGRAM_CONSTANTS,
-      .brw   = (BRW_NEW_CURBE_OFFSETS |
-               BRW_NEW_FRAGMENT_PROGRAM |
+      .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
                BRW_NEW_PS_BINDING_TABLE |
-               BRW_NEW_URB_FENCE |
                BRW_NEW_BATCH),
       .cache = (CACHE_NEW_SAMPLER |
                CACHE_NEW_WM_PROG)