upload_wm_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
+ /* BRW_NEW_FRAGMENT_PROGRAM */
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw->fragment_program);
- bool writes_depth = false;
+ /* BRW_NEW_FS_PROG_DATA */
+ const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
+ bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
uint32_t dw1, dw2;
/* _NEW_BUFFERS */
if (ctx->Polygon.StippleFlag)
dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
- /* BRW_NEW_FRAGMENT_PROGRAM */
if (fp->program.Base.InputsRead & VARYING_BIT_POS)
dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
- if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
- writes_depth = fp->program.FragDepthLayout != FRAG_DEPTH_LAYOUT_UNCHANGED;
-
- switch (fp->program.FragDepthLayout) {
- case FRAG_DEPTH_LAYOUT_NONE:
- case FRAG_DEPTH_LAYOUT_ANY:
- dw1 |= GEN7_WM_PSCDEPTH_ON;
- break;
- case FRAG_DEPTH_LAYOUT_GREATER:
- dw1 |= GEN7_WM_PSCDEPTH_ON_GE;
- break;
- case FRAG_DEPTH_LAYOUT_LESS:
- dw1 |= GEN7_WM_PSCDEPTH_ON_LE;
- break;
- case FRAG_DEPTH_LAYOUT_UNCHANGED:
- break;
- }
- }
- /* CACHE_NEW_WM_PROG */
- dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
+
+ dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT;
+ dw1 |= prog_data->barycentric_interp_modes <<
GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
/* _NEW_COLOR, _NEW_MULTISAMPLE */
/* Enable if the pixel shader kernel generates and outputs oMask.
*/
- if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||
+ if (prog_data->uses_kill || ctx->Color.AlphaEnabled ||
ctx->Multisample.SampleAlphaToCoverage ||
- brw->wm.prog_data->uses_omask) {
+ prog_data->uses_omask) {
dw1 |= GEN7_WM_KILL_ENABLE;
}
const struct brw_tracked_state gen7_wm_state = {
.dirty = {
- .mesa = (_NEW_LINE | _NEW_POLYGON |
- _NEW_COLOR | _NEW_BUFFERS |
- _NEW_MULTISAMPLE),
- .brw = (BRW_NEW_FRAGMENT_PROGRAM |
- BRW_NEW_BATCH),
- .cache = CACHE_NEW_WM_PROG,
+ .mesa = _NEW_BUFFERS |
+ _NEW_COLOR |
+ _NEW_LINE |
+ _NEW_MULTISAMPLE |
+ _NEW_POLYGON,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_FRAGMENT_PROGRAM |
+ BRW_NEW_FS_PROG_DATA,
},
.emit = upload_wm_state,
};
const int max_threads_shift = brw->is_haswell ?
HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
+ /* BRW_NEW_FS_PROG_DATA */
+ const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
+
dw2 = dw4 = dw5 = ksp2 = 0;
dw2 |=
(ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
- /* CACHE_NEW_WM_PROG */
- dw2 |= ((brw->wm.prog_data->base.binding_table.size_bytes / 4) <<
+ dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
- /* Use ALT floating point mode for ARB fragment programs, because they
- * require 0^0 == 1. Even though _CurrentFragmentProgram is used for
- * rendering, CurrentProgram[MESA_SHADER_FRAGMENT] is used for this check
- * to differentiate between the GLSL and non-GLSL cases.
- */
- /* BRW_NEW_FRAGMENT_PROGRAM */
- if (ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
+ if (prog_data->base.use_alt_mode)
dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
/* Haswell requires the sample mask to be set in this packet as well as
dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
- /* CACHE_NEW_WM_PROG */
- if (brw->wm.prog_data->base.nr_params > 0)
+ if (prog_data->base.nr_params > 0)
dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
/* From the IVB PRM, volume 2 part 1, page 287:
* Target Write messages. If present, the oMask data is used to mask off
* samples."
*/
- if (brw->wm.prog_data->uses_omask)
+ if (prog_data->uses_omask)
dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;
/* From the IVB PRM, volume 2 part 1, page 287:
* We only require XY sample offsets. So, this recommendation doesn't
* look useful at the moment. We might need this in future.
*/
- if (brw->wm.prog_data->uses_pos_offset)
+ if (prog_data->uses_pos_offset)
dw4 |= GEN7_PS_POSOFFSET_SAMPLE;
else
dw4 |= GEN7_PS_POSOFFSET_NONE;
- /* CACHE_NEW_WM_PROG | _NEW_COLOR
+ /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR
*
* The hardware wedges if you have this bit set but don't turn on any dual
* source blend factors.
*/
- if (brw->wm.prog_data->dual_src_blend &&
+ if (prog_data->dual_src_blend &&
(ctx->Color.BlendEnabled & 1) &&
ctx->Color.Blend[0]._UsesDualSrc) {
dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
}
- /* CACHE_NEW_WM_PROG */
- if (brw->wm.prog_data->num_varying_inputs != 0)
+ /* BRW_NEW_FS_PROG_DATA */
+ if (prog_data->num_varying_inputs != 0)
dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
/* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
assert(min_inv_per_frag >= 1);
- if (brw->wm.prog_data->prog_offset_16 || brw->wm.prog_data->no_8) {
+ if (prog_data->prog_offset_16 || prog_data->no_8) {
dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
- if (!brw->wm.prog_data->no_8 && min_inv_per_frag == 1) {
+ if (!prog_data->no_8 && min_inv_per_frag == 1) {
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
- dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
+ dw5 |= (prog_data->base.dispatch_grf_start_reg <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
- dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
+ dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
ksp0 = brw->wm.base.prog_offset;
- ksp2 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
+ ksp2 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
} else {
- dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
+ dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
- ksp0 = brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16;
+ ksp0 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
}
}
else {
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
- dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
+ dw5 |= (prog_data->base.dispatch_grf_start_reg <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
ksp0 = brw->wm.base.prog_offset;
}
OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
OUT_BATCH(ksp0);
OUT_BATCH(dw2);
- if (brw->wm.prog_data->base.total_scratch) {
+ if (prog_data->base.total_scratch) {
OUT_RELOC(brw->wm.base.scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- ffs(brw->wm.prog_data->base.total_scratch) - 11);
+ ffs(prog_data->base.total_scratch) - 11);
} else {
OUT_BATCH(0);
}
const struct brw_tracked_state gen7_ps_state = {
.dirty = {
- .mesa = (_NEW_COLOR |
- _NEW_BUFFERS |
- _NEW_MULTISAMPLE),
- .brw = (BRW_NEW_FRAGMENT_PROGRAM |
- BRW_NEW_BATCH),
- .cache = (CACHE_NEW_WM_PROG)
+ .mesa = _NEW_BUFFERS |
+ _NEW_COLOR |
+ _NEW_MULTISAMPLE,
+ .brw = BRW_NEW_BATCH |
+ BRW_NEW_FRAGMENT_PROGRAM |
+ BRW_NEW_FS_PROG_DATA,
},
.emit = upload_ps_state,
};
projects / mesa.git / blobdiff