const struct brw_fragment_program *fp =
brw_fragment_program_const(brw->fragment_program);
bool writes_depth = false;
- uint32_t dw1;
+ uint32_t dw1, dw2;
- dw1 = 0;
+ /* _NEW_BUFFERS */
+ bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
+
+ dw1 = dw2 = 0;
dw1 |= GEN7_WM_STATISTICS_ENABLE;
dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
/* BRW_NEW_FRAGMENT_PROGRAM */
- if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
+ if (fp->program.Base.InputsRead & VARYING_BIT_POS)
dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
writes_depth = true;
dw1 |= GEN7_WM_PSCDEPTH_ON;
}
+ /* CACHE_NEW_WM_PROG */
+ dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
+ GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
- /* _NEW_COLOR */
- if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
+ /* _NEW_COLOR, _NEW_MULTISAMPLE */
+ if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||
+ ctx->Multisample.SampleAlphaToCoverage)
dw1 |= GEN7_WM_KILL_ENABLE;
/* _NEW_BUFFERS */
dw1 & GEN7_WM_KILL_ENABLE) {
dw1 |= GEN7_WM_DISPATCH_ENABLE;
}
-
- dw1 |= brw_compute_barycentric_interp_modes() <<
- GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
+ if (multisampled_fbo) {
+ /* _NEW_MULTISAMPLE */
+ if (ctx->Multisample.Enabled)
+ dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
+ else
+ dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
+ dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
+ } else {
+ dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
+ dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
+ }
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
OUT_BATCH(dw1);
- OUT_BATCH(0);
+ OUT_BATCH(dw2);
ADVANCE_BATCH();
}
const struct brw_tracked_state gen7_wm_state = {
.dirty = {
.mesa = (_NEW_LINE | _NEW_POLYGON |
- _NEW_COLOR | _NEW_BUFFERS),
+ _NEW_COLOR | _NEW_BUFFERS |
+ _NEW_MULTISAMPLE),
.brw = (BRW_NEW_FRAGMENT_PROGRAM |
- BRW_NEW_URB_FENCE |
BRW_NEW_BATCH),
- .cache = 0,
+ .cache = CACHE_NEW_WM_PROG,
},
.emit = upload_wm_state,
};
upload_ps_state(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &intel->ctx;
uint32_t dw2, dw4, dw5;
+ const int max_threads_shift = brw->intel.is_haswell ?
+ HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
+ /* BRW_NEW_PS_BINDING_TABLE */
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
OUT_BATCH(brw->wm.bind_bo_offset);
/* CACHE_NEW_SAMPLER */
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
- OUT_BATCH(brw->wm.sampler_offset);
+ OUT_BATCH(brw->sampler.offset);
ADVANCE_BATCH();
/* CACHE_NEW_WM_PROG */
brw->wm.prog_data->dispatch_width) / 8);
OUT_BATCH(0);
/* Pointer to the WM constant buffer. Covered by the set of
- * state flags from gen7_prepare_wm_constants
+ * state flags from gen6_upload_wm_push_constants.
*/
OUT_BATCH(brw->wm.push_const_offset);
OUT_BATCH(0);
dw2 = dw4 = dw5 = 0;
- dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
+ /* CACHE_NEW_SAMPLER */
+ dw2 |= (ALIGN(brw->sampler.count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
- /* BRW_NEW_NR_WM_SURFACES */
- dw2 |= brw->wm.nr_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT;
+ /* Use ALT floating point mode for ARB fragment programs, because they
+ * require 0^0 == 1. Even though _CurrentFragmentProgram is used for
+ * rendering, CurrentFragmentProgram is used for this check to
+ * differentiate between the GLSL and non-GLSL cases.
+ */
+ if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
+ dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
- /* OpenGL non-ieee floating point mode */
- dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
+ if (intel->is_haswell)
+ dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
- /* CACHE_NEW_SAMPLER */
- dw4 |= (brw->max_wm_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT;
+ dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
/* CACHE_NEW_WM_PROG */
if (brw->wm.prog_data->nr_params > 0)
dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
+ /* CACHE_NEW_WM_PROG | _NEW_COLOR
+ *
+ * The hardware wedges if you have this bit set but don't turn on any dual
+ * source blend factors.
+ */
+ if (brw->wm.prog_data->dual_src_blend &&
+ (ctx->Color.BlendEnabled & 1) &&
+ ctx->Color.Blend[0]._UsesDualSrc) {
+ dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
+ }
+
/* BRW_NEW_FRAGMENT_PROGRAM */
if (brw->fragment_program->Base.InputsRead != 0)
dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
- if (brw->wm.prog_data->dispatch_width == 8)
- dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
- else
+ dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
+ if (brw->wm.prog_data->prog_offset_16)
dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
- /* BRW_NEW_CURBE_OFFSETS */
dw5 |= (brw->wm.prog_data->first_curbe_grf <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+ dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+ GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
BEGIN_BATCH(8);
OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
const struct brw_tracked_state gen7_ps_state = {
.dirty = {
- .mesa = _NEW_PROGRAM_CONSTANTS,
- .brw = (BRW_NEW_CURBE_OFFSETS |
- BRW_NEW_FRAGMENT_PROGRAM |
- BRW_NEW_NR_WM_SURFACES |
+ .mesa = (_NEW_PROGRAM_CONSTANTS |
+ _NEW_COLOR),
+ .brw = (BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_PS_BINDING_TABLE |
- BRW_NEW_URB_FENCE |
BRW_NEW_BATCH),
.cache = (CACHE_NEW_SAMPLER |
CACHE_NEW_WM_PROG)
projects / mesa.git / blobdiff