upload_wm_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
- /* BRW_NEW_FRAGMENT_PROGRAM */
- const struct brw_fragment_program *fp =
- brw_fragment_program_const(brw->fragment_program);
/* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
+ const struct brw_wm_prog_data *prog_data =
+ brw_wm_prog_data(brw->wm.base.prog_data);
bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
uint32_t dw1, dw2;
if (ctx->Polygon.StippleFlag)
dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
- if (fp->program.Base.InputsRead & VARYING_BIT_POS)
- dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
+ if (prog_data->uses_src_depth)
+ dw1 |= GEN7_WM_USES_SOURCE_DEPTH;
+
+ if (prog_data->uses_src_w)
+ dw1 |= GEN7_WM_USES_SOURCE_W;
dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT;
dw1 |= prog_data->barycentric_interp_modes <<
GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
- /* _NEW_COLOR, _NEW_MULTISAMPLE */
+ /* _NEW_COLOR, _NEW_MULTISAMPLE _NEW_BUFFERS */
/* Enable if the pixel shader kernel generates and outputs oMask.
*/
- if (prog_data->uses_kill || ctx->Color.AlphaEnabled ||
- ctx->Multisample.SampleAlphaToCoverage ||
+ if (prog_data->uses_kill ||
+ _mesa_is_alpha_test_enabled(ctx) ||
+ _mesa_is_alpha_to_coverage_enabled(ctx) ||
prog_data->uses_omask) {
dw1 |= GEN7_WM_KILL_ENABLE;
}
- if (_mesa_active_fragment_shader_has_atomic_ops(&brw->ctx)) {
- dw1 |= GEN7_WM_DISPATCH_ENABLE;
- }
-
/* _NEW_BUFFERS | _NEW_COLOR */
if (brw_color_buffer_write_enabled(brw) || writes_depth ||
- prog_data->base.nr_image_params ||
- dw1 & GEN7_WM_KILL_ENABLE) {
+ prog_data->has_side_effects || dw1 & GEN7_WM_KILL_ENABLE) {
dw1 |= GEN7_WM_DISPATCH_ENABLE;
}
if (multisampled_fbo) {
else
dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
- if (_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false) > 1)
+ if (prog_data->persample_dispatch)
dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
else
dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
}
- if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
+ if (prog_data->uses_sample_mask) {
dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK;
}
+ /* BRW_NEW_FS_PROG_DATA */
+ if (prog_data->early_fragment_tests)
+ dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
+ else if (prog_data->has_side_effects)
+ dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
+
+ /* The "UAV access enable" bits are unnecessary on HSW because they only
+ * seem to have an effect on the HW-assisted coherency mechanism which we
+ * don't need, and the rasterization-related UAV_ONLY flag and the
+ * DISPATCH_ENABLE bit can be set independently from it.
+ * C.f. gen8_upload_ps_extra().
+ *
+ * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS | _NEW_COLOR
+ */
+ if (brw->is_haswell &&
+ !(brw_color_buffer_write_enabled(brw) || writes_depth) &&
+ prog_data->has_side_effects)
+ dw2 |= HSW_WM_UAV_ONLY;
+
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
OUT_BATCH(dw1);
_NEW_MULTISAMPLE |
_NEW_POLYGON,
.brw = BRW_NEW_BATCH |
- BRW_NEW_FRAGMENT_PROGRAM |
+ BRW_NEW_BLORP |
BRW_NEW_FS_PROG_DATA,
},
.emit = upload_wm_state,
static void
gen7_upload_ps_state(struct brw_context *brw,
- const struct gl_fragment_program *fp,
const struct brw_stage_state *stage_state,
const struct brw_wm_prog_data *prog_data,
bool enable_dual_src_blend, unsigned sample_mask,
unsigned fast_clear_op)
{
- struct gl_context *ctx = &brw->ctx;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
uint32_t dw2, dw4, dw5, ksp0, ksp2;
const int max_threads_shift = brw->is_haswell ?
HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
if (brw->is_haswell)
dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK);
- dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
+ dw4 |= (devinfo->max_wm_threads - 1) << max_threads_shift;
if (prog_data->base.nr_params > 0)
dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
if (prog_data->num_varying_inputs != 0)
dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
- /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
- * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
- * is successfully compiled. In majority of the cases that bring us
- * better performance than 'SIMD8 only' dispatch.
- */
- int min_inv_per_frag =
- _mesa_get_min_invocations_per_fragment(ctx, fp, false);
- assert(min_inv_per_frag >= 1);
+ dw4 |= fast_clear_op;
- if (prog_data->prog_offset_16 || prog_data->no_8) {
+ if (prog_data->dispatch_16)
dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
- if (!prog_data->no_8 && min_inv_per_frag == 1) {
- dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
- dw5 |= (prog_data->base.dispatch_grf_start_reg <<
- GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
- dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
- GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
- ksp0 = stage_state->prog_offset;
- ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
- } else {
- dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
- GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
- ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
- }
- }
- else {
+
+ if (prog_data->dispatch_8)
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
- dw5 |= (prog_data->base.dispatch_grf_start_reg <<
- GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
- ksp0 = stage_state->prog_offset;
- }
- dw4 |= fast_clear_op;
+ dw5 |= prog_data->base.dispatch_grf_start_reg <<
+ GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
+ dw5 |= prog_data->dispatch_grf_start_reg_2 <<
+ GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
+
+ ksp0 = stage_state->prog_offset;
+ ksp2 = stage_state->prog_offset + prog_data->prog_offset_2;
BEGIN_BATCH(8);
OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
if (prog_data->base.total_scratch) {
OUT_RELOC(brw->wm.base.scratch_bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- ffs(prog_data->base.total_scratch) - 11);
+ ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
}
upload_ps_state(struct brw_context *brw)
{
/* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
+ const struct brw_wm_prog_data *prog_data =
+ brw_wm_prog_data(brw->wm.base.prog_data);
const struct gl_context *ctx = &brw->ctx;
/* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
const bool enable_dual_src_blend = prog_data->dual_src_blend &&
const unsigned sample_mask =
brw->is_haswell ? gen6_determine_sample_mask(brw) : 0;
- gen7_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data,
+ gen7_upload_ps_state(brw, &brw->wm.base, prog_data,
enable_dual_src_blend, sample_mask,
brw->wm.fast_clear_op);
}
_NEW_COLOR |
_NEW_MULTISAMPLE,
.brw = BRW_NEW_BATCH |
- BRW_NEW_FRAGMENT_PROGRAM |
+ BRW_NEW_BLORP |
BRW_NEW_FS_PROG_DATA,
},
.emit = upload_ps_state,
projects / mesa.git / blobdiff