static void
upload_wm_state(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
const struct brw_fragment_program *fp =
brw_fragment_program_const(brw->fragment_program);
bool writes_depth = false;
static void
upload_ps_state(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
uint32_t dw2, dw4, dw5;
- const int max_threads_shift = intel->is_haswell ?
+ const int max_threads_shift = brw->is_haswell ?
HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
/* BRW_NEW_PS_BINDING_TABLE */
/* CACHE_NEW_SAMPLER */
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
- OUT_BATCH(brw->sampler.offset);
+ OUT_BATCH(brw->wm.sampler_offset);
ADVANCE_BATCH();
/* CACHE_NEW_WM_PROG */
/* Pointer to the WM constant buffer. Covered by the set of
* state flags from gen6_upload_wm_push_constants.
*/
- OUT_BATCH(brw->wm.push_const_offset);
+ OUT_BATCH(brw->wm.push_const_offset | GEN7_MOCS_L3);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
dw2 = dw4 = dw5 = 0;
/* CACHE_NEW_SAMPLER */
- dw2 |= (ALIGN(brw->sampler.count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
+ dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
/* Use ALT floating point mode for ARB fragment programs, because they
* require 0^0 == 1. Even though _CurrentFragmentProgram is used for
if (ctx->Shader.CurrentFragmentProgram == NULL)
dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
- if (intel->is_haswell)
+ if (brw->is_haswell)
dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;