mesa: add/update comments in _mesa_copy_buffer_subdata()

[mesa.git] / src / mesa / drivers / dri / i965 / gen7_wm_surface_state.c

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 7084bdc3ef3b6734cc14c14aa1d74ff948debf0b..1c0183b70c1e8497863312d71175b4e06b5bca68 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -59,6 +59,7 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
    struct brw_context *brw = brw_context(ctx);
    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
    struct intel_texture_object *intelObj = intel_texture_object(tObj);
+   struct intel_mipmap_tree *mt = intelObj->mt;
    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
@@ -71,8 +72,11 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
                          sizeof(*surf), 32, &brw->bind.surf_offset[surf_index]);
    memset(surf, 0, sizeof(*surf));
 
+   if (mt->align_h == 4)
+      surf->ss0.vertical_alignment = 1;
+
    surf->ss0.surface_type = translate_tex_target(tObj->Target);
-   surf->ss0.surface_format = translate_tex_format(firstImage->TexFormat,
+   surf->ss0.surface_format = translate_tex_format(mt->format,
                                                    firstImage->InternalFormat,
                                                    sampler->DepthMode,
                                                    sampler->sRGBDecode);
@@ -85,10 +89,11 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
       surf->ss0.cube_neg_z = 1;
    }
 
+   surf->ss0.is_array = depth > 1 && tObj->Target != GL_TEXTURE_3D;
+
    gen7_set_surface_tiling(surf, intelObj->mt->region->tiling);
 
    /* ss0 remaining fields:
-    * - is_array
     * - vertical_alignment
     * - horizontal_alignment
     * - vert_line_stride (exists on gen6 but we ignore it)
@@ -200,25 +205,10 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
                          sizeof(*surf), 32, &brw->bind.surf_offset[unit]);
    memset(surf, 0, sizeof(*surf));
 
+   if (irb->mt->align_h == 4)
+      surf->ss0.vertical_alignment = 1;
+
    switch (irb->Base.Format) {
-   case MESA_FORMAT_XRGB8888:
-      /* XRGB is handled as ARGB because the chips in this family
-       * cannot render to XRGB targets.  This means that we have to
-       * mask writes to alpha (ala glColorMask) and reconfigure the
-       * alpha blending hardware to use GL_ONE (or GL_ZERO) for
-       * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
-       * used.
-       */
-      surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
-      break;
-   case MESA_FORMAT_INTENSITY_FLOAT32:
-   case MESA_FORMAT_LUMINANCE_FLOAT32:
-      /* For these formats, we just need to read/write the first
-       * channel into R, which is to say that we just treat them as
-       * GL_RED.
-       */
-      surf->ss0.surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
-      break;
    case MESA_FORMAT_SARGB8:
       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
         surfaces to the blend/update as sRGB */
@@ -229,7 +219,12 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
       break;
    default:
       assert(brw_render_target_supported(intel, irb->Base.Format));
-      surf->ss0.surface_format = brw_format_for_mesa_format(irb->Base.Format);
+      surf->ss0.surface_format = brw->render_target_format[irb->Base.Format];
+      if (unlikely(!brw->format_supported_as_render_target[irb->Base.Format])) {
+        _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
+                      __FUNCTION__, _mesa_get_format_name(irb->Base.Format));
+      }
+       break;
    }
 
    surf->ss0.surface_type = BRW_SURFACE_2D;